公开(公告)号：US12159142B1

公开(公告)日：2024-12-03

申请号：US18310919

申请日：2023-05-02

Applicant: Apple Inc.

Inventor： Yuan C. Chou ,  Chang Xu ,  Deepankar Duggal ,  Debasish Chandra

IPC: G06F9/30 ,  G06F9/38

Abstract: Techniques are disclosed relating to predicting values for load operations. In some embodiments, front-end circuitry is configured to predict values of load operations based on multiple value tagged geometric length predictor (VTAGE) prediction tables (based on program counter information and branch history information). Training circuitry may adjust multiple VTAGE learning tables based on completed load operations. Control circuitry may pre-compute access information (e.g., an index) for a VTAGE learning table for a load based on branch history information that is available to the front-end circuitry but that is unavailable to the training circuitry, store the pre-computed access information, and provide the pre-computed access information from the first storage circuitry to the training circuitry to access the VTAGE learning table based on completion of the load. This may facilitate VTAGE training without pipelining the branch history information.

公开(公告)号：US20240362027A1

公开(公告)日：2024-10-31

申请号：US18764611

申请日：2024-07-05

Applicant: Apple Inc.

Inventor： Yuan C. Chou ,  Debasish Chandra ,  Mridul Agarwal ,  Haoyan Jia

IPC: G06F9/38

CPC classification number: G06F9/3842 ,  G06F9/383 ,  G06F9/3832

Abstract: Techniques are disclosed relating to load value prediction. In some embodiments, a processor includes load address prediction circuitry and load value prediction circuitry. Training circuitry may train loads in a given entry, and may include a first entry configured to store first predicted load address information and a confidence indication of confidence that the first predicted load address information is correct and a second entry configured to store first predicted load value information and a confidence indication of confidence that the first predicted load value information is correct (note a given entry may be configured to load or value prediction at different times). Control circuitry may, in response to an entry in the training circuitry reaching a threshold level of confidence, allocate a corresponding entry in either the load value prediction circuitry or the load address prediction circuitry.

公开(公告)号：US20240354109A1

公开(公告)日：2024-10-24

申请号：US18305151

申请日：2023-04-21

Applicant: Apple Inc.

Inventor： Yuan C. Chou ,  Deepankar Duggal ,  Debasish Chandra ,  Niket K. Choudhary ,  Richard F. Russo

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3802 ,  G06F9/30043 ,  G06F9/3016 ,  G06F9/3861

Abstract: Disclosed techniques relate to re-use of speculative results from an incorrect execution path. In some embodiments, when a control transfer instruction is mispredicted, a load instruction may have been executed on the wrong path. In disclosed embodiments, result storage circuitry records information that indicates destination registers of speculatively-executed load instructions including a first load instruction. Control flow tracker circuitry may store information indicating a reconvergence point for the control transfer instruction. Re-use control circuitry may track registers written by instructions prior to the reconvergence point, determine that the first load instruction does not depend on data from any instruction between the control transfer instruction and the reconvergence point, and use, as a result of the first load instruction, a value from a recorded destination register that was written based on speculative execution of the first load, notwithstanding the misprediction of the control transfer instruction.

公开(公告)号：US12175248B2

公开(公告)日：2024-12-24

申请号：US18305151

申请日：2023-04-21

Applicant: Apple Inc.

Inventor： Yuan C. Chou ,  Deepankar Duggal ,  Debasish Chandra ,  Niket K Choudhary ,  Richard F. Russo

IPC: G06F9/38 ,  G06F9/30

Abstract: Disclosed techniques relate to re-use of speculative results from an incorrect execution path. In some embodiments, when a control transfer instruction is mispredicted, a load instruction may have been executed on the wrong path. In disclosed embodiments, result storage circuitry records information that indicates destination registers of speculatively-executed load instructions including a first load instruction. Control flow tracker circuitry may store information indicating a reconvergence point for the control transfer instruction. Re-use control circuitry may track registers written by instructions prior to the reconvergence point, determine that the first load instruction does not depend on data from any instruction between the control transfer instruction and the reconvergence point, and use, as a result of the first load instruction, a value from a recorded destination register that was written based on speculative execution of the first load, notwithstanding the misprediction of the control transfer instruction.

公开(公告)号：US20240354111A1

公开(公告)日：2024-10-24

申请号：US18305173

申请日：2023-04-21

Applicant: Apple Inc.

Inventor： Yuan C. Chou ,  Deepankar Duggal ,  Debasish Chandra ,  Niket K. Choudhary ,  Richard F. Russo

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3842 ,  G06F9/3005 ,  G06F9/3016

Abstract: Disclosed techniques relate to re-use of speculative results from an incorrect execution path. In some embodiments, when a first control transfer instruction is mispredicted, a second control transfer instruction may have been executed on the wrong path because of the misprediction. Result storage circuitry may record information indicating a determined direction for the second control transfer instruction. Control flow tracker circuitry may store, for the first control transfer instruction, information indicating a reconvergence point. Re-use control circuitry may track registers written by instructions prior to the reconvergence point, determine, based on the tracked registers, that the second control transfer instruction does not depend on data from any instruction between the first control transfer instruction and the reconvergence point, and use the recorded determined direction for the second control transfer instruction, notwithstanding the misprediction of the first control transfer instruction.

公开(公告)号：US12067398B1

公开(公告)日：2024-08-20

申请号：US17661491

申请日：2022-04-29

Applicant: Apple Inc.

Inventor： Yuan C. Chou ,  Debasish Chandra ,  Mridul Agarwal ,  Haoyan Jia

IPC: G06F9/38

CPC classification number: G06F9/3842 ,  G06F9/383 ,  G06F9/3832

Abstract: Techniques are disclosed relating to load value prediction. In some embodiments, a processor includes learning table circuitry that is shared for both address and value prediction. Loads may be trained for value prediction when they are eligible for both value and address prediction. Entries in the learning table may be promoted to an address prediction table or a load value prediction table for prediction, e.g., when they reach a threshold confidence level in the training table. In some embodiments, the learning table stores a hash of a predicted load value and control circuitry uses a probing load to retrieve the actual predicted load value for the value prediction table.