公开(公告)号：US20180246723A1

公开(公告)日：2018-08-30

申请号：US15441604

申请日：2017-02-24

申请人： International Business Machines Corporation

发明人： Brian R. Prasky ,  David A. Schroter ,  Chung-Lung K. Shum ,  Corey C. Stappenbeck

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/32

CPC分类号： G06F9/30043 ,  G06F9/30021 ,  G06F9/30058 ,  G06F9/30098 ,  G06F9/32 ,  G06F9/3832 ,  G06F9/3834 ,  G06F9/384 ,  G06F9/3842

摘要： Systems, methods, and computer-readable media are disclosed for executing a predicted load that bypasses memory access for a load instruction. A first physical register that is predicted as storing a value to be loaded by the load instruction is identified and the value stored in the first physical register is copied to a second physical register for use by a consumer operation. A predicted store instruction corresponding to the load instruction is identified and a mapping table is accessed to obtain data associated with the predicted store instruction. The data is evaluated to determine whether the predicted load meets dependency constraints. As a result of execution of the predicted load, the consumer operation can utilize the data stored in the first physical register directly and bypass the cache memory access that would otherwise be required to execute the load instruction.

公开(公告)号：US10061584B2

公开(公告)日：2018-08-28

申请号：US15060404

申请日：2016-03-03

申请人： Microsoft Technology Licensing, LLC

发明人： Douglas C. Burger ,  Aaron L. Smith

IPC分类号： G06F9/312 ,  G06F9/44 ,  G06F9/30 ,  G06F15/80 ,  G06F9/32 ,  G06F9/38 ,  G06F9/26 ,  G06F11/36 ,  G06F12/0862 ,  G06F9/35 ,  G06F12/1009 ,  G06F13/42 ,  G06F15/78 ,  G06F9/46 ,  G06F9/52 ,  G06F12/0875 ,  G06F12/0811 ,  G06F12/0806

CPC分类号： G06F9/3016 ,  G06F9/268 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/32 ,  G06F9/321 ,  G06F9/345 ,  G06F9/35 ,  G06F9/355 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3848 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/466 ,  G06F9/528 ,  G06F11/36 ,  G06F11/3648 ,  G06F11/3656 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/4221 ,  G06F15/7867 ,  G06F15/80 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/604 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： Apparatus and methods are disclosed for nullifying memory store instructions identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions, based on a target field of the nullification instruction. The memory access instruction associated with the instruction identification is nullified. The memory access instruction is in a first instruction block of the plurality of instruction blocks. Based on the nullified memory access instruction, a subsequent memory access instruction from the first instruction block is executed.

公开(公告)号：US10013255B2

公开(公告)日：2018-07-03

申请号：US15077936

申请日：2016-03-23

申请人： Centipede Semi Ltd.

发明人： Jonathan Friedmann ,  Ido Goren ,  Shay Koren ,  Noam Mizrahi ,  Alberto Mandler

IPC分类号： G06F9/38 ,  G06F9/40 ,  G06F9/45 ,  G06F9/30 ,  G06F8/41 ,  G06F9/455

CPC分类号： G06F9/30058 ,  G06F8/443 ,  G06F9/30061 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/30079 ,  G06F9/3808 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3867 ,  G06F9/45516

摘要： A method includes, in a processor, processing a sequence of pre-compiled instructions by an instruction pipeline of the processor. A first block of instructions is identified in the instructions flowing via the pipeline. The first block includes a conditional branch instruction that conditionally diverges execution of the instructions into at least first and second flow-control traces that differ from one another in multiple instructions and converge at a given instruction that is again common to the first and second flow-control traces. A second block of instructions, which is logically equivalent to the first block but replaces the first and second flow-control traces by a single flow-control trace, is created by the processor at runtime. The pipeline is caused to execute the second block instead of the first block.

公开(公告)号：US10001996B2

公开(公告)日：2018-06-19

申请号：US13662171

申请日：2012-10-26

申请人： NVIDIA Corporation

发明人： Magnus Ekman ,  James van Zoeren ,  Paul Serris

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F11/30 ,  G06F11/34

CPC分类号： G06F9/30189 ,  G06F9/3842 ,  G06F11/3024 ,  G06F11/3409 ,  G06F2201/885

摘要： Embodiments related to selecting a runahead poison policy from a plurality of runahead poison policies during microprocessor operation are provided. The example method includes causing the microprocessor to enter runahead upon detection of a runahead event and implementing a first runahead poison policy selected from a plurality of runahead poison policies operative to manage runahead poison injection during runahead. The example method also includes during microprocessor operation, selecting a second runahead poison policy operative to manage runahead poison injection differently from the first runahead poison policy.

公开(公告)号：US09983875B2

公开(公告)日：2018-05-29

申请号：US15060690

申请日：2016-03-04

申请人： International Business Machines Corporation

发明人： Sundeep Chadha ,  David A. Hrusecky ,  Elizabeth A. McGlone ,  Jennifer L. Molnar

IPC分类号： G06F9/312 ,  G06F9/40 ,  G06F13/40 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30043 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3832 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3867 ,  G06F9/3871 ,  G06F13/4068

摘要： Operation of a multi-slice processor that includes a plurality of execution slices, a plurality of load/store slices, and an instruction sequencing unit, where operation includes: receiving, at a load/store slice, a load instruction to be issued; determining, at the load/store slice, that the load instruction has not completed and is to be reissued; and responsive to determining that the load instruction is to be reissued, delaying a signal, from the load/store slice to the instruction sequencing unit, that allows the instruction sequencing unit to issue one or more instructions dependent upon the load instruction.

公开(公告)号：US20180129500A1

公开(公告)日：2018-05-10

申请号：US15616970

申请日：2017-06-08

申请人： Centipede Semi Ltd.

发明人： Shay Koren ,  Noam Mizrahi ,  Jonathan Friedmann

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30058 ,  G06F9/30065 ,  G06F9/30105 ,  G06F9/3016 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3808 ,  G06F9/381 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3859

摘要： A method includes retrieving to a pipeline of a processor first instructions of program code from a first region in the program code. Before fully determining a flow-control path, which is to be traversed within the first region until exit from the first region, a beginning of a second region in the code that is to be processed following the first region is predicted, and second instructions begin to be retrieved to the pipeline from the second region. The retrieved first instructions and second instructions are processed by the pipeline.

公开(公告)号：US20180121273A1

公开(公告)日：2018-05-03

申请号：US15338247

申请日：2016-10-28

申请人： NVIDIA CORPORATION

发明人： Nick Fortino ,  Fred Gruner ,  Ben Hertzberg

IPC分类号： G06F11/07 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F11/079 ,  G06F9/30174 ,  G06F9/3842 ,  G06F9/3859 ,  G06F9/3863 ,  G06F11/0721 ,  G06F11/0751 ,  G06F11/0793 ,  G06F11/36

摘要： Systems and methods for enhancing reliability are presented. In one embodiment, a system comprises a processor configured to execute program instructions and contemporaneously perform reliability enhancement operations (e.g., fault checking, error mitigation, etc.) incident to executing the program instructions. The fault checking can include: identifying functionality of a particular portion of the program instructions; speculatively executing multiple sets of operations contemporaneously; and comparing execution results from the multiple sets of operations. The multiple sets of operations are functional duplicates of the particular portion of the program instructions. If the execution results have a matching value, then the value can be made architecturally visible. If the execution results do not have a matching value, the system can be put in a safe mode. An error mitigation operation can be performed can include a corrective procedure. The corrective procedure can include rollback to a known valid state.

公开(公告)号：US20180121204A1

公开(公告)日：2018-05-03

申请号：US15845641

申请日：2017-12-18

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Jaewoong CHUNG ,  David S. CHRISTIE ,  Michael P. HOHMUTH ,  Stephan DIESTELHORST ,  Martin POHLACK ,  Luke YEN

IPC分类号： G06F9/38 ,  G06F9/46 ,  G06F9/30

CPC分类号： G06F9/3842 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/467

摘要： A processing core of a plurality of processing cores is configured to execute a speculative region of code a single atomic memory transaction with respect one or more others of the plurality of processing cores. In response to determining an abort condition for issued one of the plurality of program instructions and in response to determining that the issued program instruction is not part of a mispredicted execution path, the processing core is configured to abort an attempt to execute the speculative region of code.

公开(公告)号：US09959123B2

公开(公告)日：2018-05-01

申请号：US14827284

申请日：2015-08-15

申请人： International Business Machines Corporation

发明人： Joshua W. Bowman ,  Sundeep Chadha ,  Michael J. Genden ,  Dhivya Jeganathan ,  Dung Q. Nguyen ,  David R. Terry ,  Eula F. Tolentino

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3836 ,  G06F9/30043 ,  G06F9/3824 ,  G06F9/3838 ,  G06F9/3842

摘要： An approach is provided is provided in which a computing system matches a writeback instruction tag (ITAG) to an entry instruction tag (ITAG) included in an issue queue entry. The writeback ITAG is provided by a first of multiple load store units. The issue queue entry includes multiple ready bits, each of which corresponds to one of the multiple load store units. In response to matching the writeback ITAG to the entry ITAG, the computer system sets a first ready bit corresponding to the first load store unit. In turn, the computing system issues an instruction corresponding to the entry ITAG based upon detecting that each of the multiple ready bits is set.

公开(公告)号：US09910672B2

公开(公告)日：2018-03-06

申请号：US15183365

申请日：2016-06-15

申请人： Imagination Technologies Limited

发明人： Hugh Jackson ,  Anand Khot

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F12/0842

CPC分类号： G06F9/30043 ,  G06F9/30145 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3842 ,  G06F12/0842

摘要： A method and load and store buffer for issuing a load instruction to a data cache. The method includes determining whether there are any unresolved store instructions in the store buffer that are older than the load instruction. If there is at least one unresolved store instruction in the store buffer older than the load instruction, it is determined whether the oldest unresolved store instruction in the store buffer is within a speculation window for the load instruction. If the oldest unresolved store instruction is within the speculation window for the load instruction, the load instruction is speculatively issued to the data cache. Otherwise, the load instruction is stalled until any unresolved store instructions outside the speculation window are resolved. The speculation window is a short window that defines a number of instructions or store instructions that immediately precede the load instruction.