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公开(公告)号:US20240354260A1
公开(公告)日:2024-10-24
申请号:US18762987
申请日:2024-07-03
Applicant: Texas Instruments Incorporated
Inventor: Timothy David Anderson , Mujibur Rahman
IPC: G06F12/1045 , G06F7/24 , G06F7/487 , G06F7/499 , G06F7/53 , G06F7/57 , G06F9/30 , G06F9/32 , G06F9/345 , G06F9/38 , G06F9/48 , G06F11/00 , G06F11/10 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F12/1009 , G06F15/78 , G06F17/16 , H03H17/06
CPC classification number: G06F12/1045 , G06F7/24 , G06F7/487 , G06F7/4876 , G06F7/49915 , G06F7/53 , G06F7/57 , G06F9/3001 , G06F9/30014 , G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/30065 , G06F9/30072 , G06F9/30098 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/32 , G06F9/345 , G06F9/3802 , G06F9/3818 , G06F9/383 , G06F9/3836 , G06F9/3851 , G06F9/3856 , G06F9/3867 , G06F9/3887 , G06F9/48 , G06F11/00 , G06F11/1048 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F12/1009 , G06F17/16 , H03H17/0664 , G06F9/30018 , G06F9/325 , G06F9/381 , G06F9/3822 , G06F11/10 , G06F15/7807 , G06F15/781 , G06F2212/452 , G06F2212/60 , G06F2212/602 , G06F2212/68
Abstract: A method for sorting of a vector in a processor is provided that includes performing, by the processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values are sorted in an order indicated by the vector sort instruction, and storing the sorted vector in a storage location.
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公开(公告)号:US20240345842A1
公开(公告)日:2024-10-17
申请号:US18754455
申请日:2024-06-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Jayasree Sankaranarayanan , Dipan Kumar Mandal
CPC classification number: G06F9/383 , G06F9/30036 , G06F9/3004 , G06F9/30043
Abstract: This disclosure is directed to the problem of paralleling random read access within a reasonably sized block of data for a vector SIMD processor. The invention sets up plural parallel look up tables, moves data from main memory to each plural parallel look up table and then employs a look up table read instruction to simultaneously move data from each parallel look up table to a corresponding part a vector destination register. This enables data processing by vector single instruction multiple data (SIMD) operations. This vector destination register load can be repeated if the tables store more used data. New data can be loaded into the original tables if appropriate. A level one memory is preferably partitioned as part data cache and part directly addressable memory. The look up table memory is stored in the directly addressable memory.
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公开(公告)号:US12118358B2
公开(公告)日:2024-10-15
申请号:US17583380
申请日:2022-01-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Son Hung Tran , Shyam Jagannathan , Timothy David Anderson
IPC: G06F9/30 , G06F9/32 , G06F9/345 , G06F9/38 , G06F11/00 , G06F11/10 , G06F12/0811 , G06F12/0875 , G06F12/0897 , G06F15/80 , G06F17/16
CPC classification number: G06F9/3016 , G06F9/30014 , G06F9/30036 , G06F9/30043 , G06F9/30098 , G06F9/30101 , G06F9/30112 , G06F9/30145 , G06F9/32 , G06F9/345 , G06F9/3802 , G06F9/383 , G06F9/3867 , G06F11/00 , G06F11/1048 , G06F12/0811 , G06F12/0875 , G06F12/0897 , G06F15/8015 , G06F9/3822 , G06F11/10 , G06F17/16 , G06F2212/452 , G06F2212/60 , G06F2212/604
Abstract: Software instructions are executed on a processor within a computer system to configure a streaming engine with stream parameters to define a multidimensional array. The stream parameters define a size for each dimension of the multidimensional array and a specified width for a selected dimension of the array. Data is fetched from a memory coupled to the streaming engine responsive to the stream parameters. A stream of vectors is formed for the multidimensional array responsive to the stream parameters from the data fetched from memory. When the selected dimension in the stream of vectors exceeds the specified width, the streaming engine inserts null elements into each portion of a respective vector for the selected dimension that exceeds the specified width in the stream of vectors. Stream vectors that are completely null are formed by the streaming engine without accessing the system memory for respective data.
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公开(公告)号:US12099400B2
公开(公告)日:2024-09-24
申请号:US18164688
申请日:2023-02-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Joseph Zbiciak , Timothy D. Anderson , Duc Bui , Kai Chirca
IPC: G06F11/00 , G06F9/30 , G06F9/345 , G06F9/38 , G06F11/07 , G06F11/27 , G06F11/30 , G06F11/36 , G06F12/0862 , G06F12/0875 , G06F13/16 , G06F11/10
CPC classification number: G06F11/0772 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/30145 , G06F9/345 , G06F9/383 , G06F9/3867 , G06F11/00 , G06F11/0721 , G06F11/073 , G06F11/27 , G06F11/3037 , G06F11/3648 , G06F12/0862 , G06F12/0875 , G06F13/1673 , G06F11/10 , G06F2212/452 , G06F2212/602
Abstract: This invention is a streaming engine employed in a digital signal processor. A fixed data stream sequence is specified by a control register. The streaming engine fetches stream data ahead of use by a central processing unit and stores it in a stream buffer. Upon occurrence of a fault reading data from memory, the streaming engine identifies the data element triggering the fault preferably storing this address in a fault address register. The streaming engine defers signaling the fault to the central processing unit until this data element is used as an operand. If the data element is never used by the central processing unit, the streaming engine never signals the fault. The streaming engine preferably stores data identifying the fault in a fault source register. The fault address register and the fault source register are preferably extended control registers accessible only via a debugger.
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公开(公告)号:US20240296065A1
公开(公告)日:2024-09-05
申请号:US18661804
申请日:2024-05-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Timothy Anderson , Joseph Zbiciak
CPC classification number: G06F9/485 , G06F9/30014 , G06F9/30047 , G06F9/30145 , G06F9/345 , G06F9/383 , G06F15/76
Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream recalled memory. Streams are started by one of two types of stream start instructions. A stream start ordinary instruction specifies a register storing a stream start address and a register of storing a stream definition template which specifies stream parameters. A stream start short-cut instruction specifies a register storing a stream start address and an implied stream definition template. A functional unit is responsive to a stream operand instruction to receive at least one operand from a stream head register. The stream template supports plural nested loops with short-cut start instructions limited to a single loop. The stream template supports data element promotion to larger data element size with sign extension or zero extension. A set of allowed stream short-cut start instructions includes various data sizes and promotion factors.
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公开(公告)号:US12072812B2
公开(公告)日:2024-08-27
申请号:US17237391
申请日:2021-04-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Timothy D. Anderson , Joseph Zbiciak , Duc Quang Bui , Abhijeet Chachad , Kai Chirca , Naveen Bhoria , Matthew D. Pierson , Daniel Wu , Ramakrishnan Venkatasubramanian
IPC: G06F9/30 , G06F7/24 , G06F7/487 , G06F7/499 , G06F7/53 , G06F7/57 , G06F9/32 , G06F9/345 , G06F9/38 , G06F9/48 , G06F11/00 , G06F11/10 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F12/1009 , G06F12/1045 , G06F17/16 , H03H17/06 , G06F15/78
CPC classification number: G06F12/1045 , G06F7/24 , G06F7/487 , G06F7/4876 , G06F7/49915 , G06F7/53 , G06F7/57 , G06F9/3001 , G06F9/30014 , G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/30065 , G06F9/30072 , G06F9/30098 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/32 , G06F9/345 , G06F9/3802 , G06F9/3818 , G06F9/383 , G06F9/3836 , G06F9/3851 , G06F9/3856 , G06F9/3867 , G06F9/3887 , G06F9/48 , G06F11/00 , G06F11/1048 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F12/1009 , G06F17/16 , H03H17/0664 , G06F9/30018 , G06F9/325 , G06F9/381 , G06F9/3822 , G06F11/10 , G06F15/7807 , G06F15/781 , G06F2212/452 , G06F2212/60 , G06F2212/602 , G06F2212/68
Abstract: Disclosed embodiments include an electronic device having a processor core, a memory, a register, and a data load unit to receive a plurality of data elements stored in the memory in response to an instruction. All of the data elements hare the same data size, which is specified by one or more coding bits. The data load unit includes an address generator to generate addresses corresponding to locations in the memory at which the data elements are located, and a formatting unit to format the data elements. The register is configured to store the formatted data elements, and the processor core is configured to receive the formatted data elements from the register.
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公开(公告)号:US11921636B2
公开(公告)日:2024-03-05
申请号:US17972675
申请日:2022-10-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Joseph Zbiciak
IPC: G06F12/08 , G06F9/30 , G06F9/345 , G06F9/38 , G06F12/0815 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F9/32 , G06F15/80
CPC classification number: G06F12/0815 , G06F9/3001 , G06F9/30036 , G06F9/30047 , G06F9/30072 , G06F9/3012 , G06F9/3013 , G06F9/30145 , G06F9/345 , G06F9/3822 , G06F9/383 , G06F9/3853 , G06F9/3887 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F9/30065 , G06F9/325 , G06F15/8007 , G06F2212/452 , G06F2212/454 , G06F2212/6026 , G06F2212/621
Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template specifies loop count and loop dimension for each nested loop. A format definition field in the stream template specifies the number of loops and the stream template bits devoted to the loop counts and loop dimensions. This permits the same bits of the stream template to be interpreted differently enabling trade off between the number of loops supported and the size of the loop counts and loop dimensions.
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公开(公告)号:US11907721B2
公开(公告)日:2024-02-20
申请号:US17379528
申请日:2021-07-19
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Asheesh Bhardwaj , Timothy David Anderson , Son Hung Tran
IPC: G06F9/30 , G06F9/38 , G06F11/10 , G06F9/32 , G06F12/0875 , G06F12/0897 , G06F11/00 , G06F9/345 , G06F17/16 , G06F7/74
CPC classification number: G06F9/3016 , G06F9/30014 , G06F9/30036 , G06F9/30098 , G06F9/30112 , G06F9/30145 , G06F9/32 , G06F9/345 , G06F9/3802 , G06F9/383 , G06F9/3867 , G06F11/00 , G06F11/1048 , G06F12/0875 , G06F12/0897 , G06F7/74 , G06F9/3822 , G06F11/10 , G06F17/16 , G06F2212/452 , G06F2212/60
Abstract: Software instructions are executed on a processor within a computer system to configure a steaming engine with stream parameters to define a multidimensional array. The stream parameters define a size for each dimension of the multidimensional array and a pad value indicator. Data is fetched from a memory coupled to the streaming engine responsive to the stream parameters. A stream of vectors is formed for the multidimensional array responsive to the stream parameters from the data fetched from memory. A padded stream vector is formed that includes a specified pad value without accessing the pad value from system memory.
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公开(公告)号:US11900117B2
公开(公告)日:2024-02-13
申请号:US17213509
申请日:2021-03-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
IPC: G06F9/30 , G06F9/38 , G06F11/10 , G06F9/32 , G06F12/0875 , G06F12/0897 , G06F11/00 , G06F9/345
CPC classification number: G06F9/3016 , G06F9/3004 , G06F9/30014 , G06F9/30036 , G06F9/30098 , G06F9/30112 , G06F9/30145 , G06F9/32 , G06F9/345 , G06F9/3802 , G06F9/383 , G06F9/3842 , G06F9/3861 , G06F9/3867 , G06F9/3877 , G06F11/00 , G06F11/1048 , G06F12/0875 , G06F12/0897 , G06F9/3822 , G06F11/10 , G06F2212/452 , G06F2212/60
Abstract: A streaming engine in a system receives a first set of stream parameters into a queue to define a first stream along with an indication of either a queue mode of operation or a speculative mode of operation for the first stream. Acquisition of the first stream then begins. At some point, a second set of stream parameters is received into the queue to define a second stream. When the queue mode of operation was specified for the first stream, the second set of parameters is queued and acquisition of the second stream is delayed until completion of acquisition of the first stream. When the speculative mode of operation was specified for the first stream, acquisition of the first stream is canceled upon receipt of the second set of stream parameters and acquisition of the second stream begins immediately.
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公开(公告)号:US11792293B2
公开(公告)日:2023-10-17
申请号:US17149752
申请日:2021-01-15
Applicant: BEIJING VOYAGER TECHNOLOGY CO., LTD.
Inventor: Fenglei Wang , Lingang Min
IPC: H04L67/568 , G06F9/54 , G06F9/48 , H04L67/1097 , G06F8/41 , G06F16/172 , G06F9/38 , G06F12/0862 , G06F12/1027 , H04W8/08 , G06F9/50
CPC classification number: H04L67/568 , G06F8/4442 , G06F9/3802 , G06F9/383 , G06F9/4881 , G06F9/5038 , G06F9/542 , G06F12/0862 , G06F12/1027 , G06F16/172 , H04L67/1097 , H04W8/082 , G06F2209/482 , G06F2209/484
Abstract: A method for data processing is provided. The method may include: preprocessing initial data to obtain preprocessed data; storing the preprocessed data; receiving a data request made through an application, the data request including information relating to a storage path of contents that are requested; in response to the data request, determining, by a nearby proxy of a first proxy cluster in a first region, whether the contents requested in the data request are cached locally; and in response to a determination that the contents are cached locally, providing, by the nearby proxy, the contents to the application; or in response to a determination that the contents are not cached locally, acquiring, by the nearby proxy, the contents based on the information relating to the storage path of the contents; and providing, by the nearby proxy, the contents to the application.
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