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公开(公告)号：US20240077932A1
公开(公告)日：2024-03-07
申请号：US18122410
申请日：2023-03-16
Applicant: Apple Inc.
Inventor： Talbott M. Houk , Wenxun Huang , Nikola Jovanovic , Floyd L. Dankert , Sanjay Pant , Alessandro Molari , Siarhei Meliukh , Nicola Florio , Ludmil N. Nikolov , Nathan F. Hanagami , Hartmut Sturm , Di Zhao , Chad L. Olson , John J. Sullivan , Seyedeh Maryam Mortazavi Zanjani , Tristan R. Hudson , Jay B. Fletcher , Jonathan A. Dutra
IPC: G06F1/3296 , G06F1/3212 , G06F1/3234
CPC classification number: G06F1/3296 , G06F1/3212 , G06F1/3278
Abstract: The present disclosure describes a system with a power management device, a wakeup circuit, a battery management device, and a connector. During a powered down mode of operation, the battery management device can provide, via the connector, a bias voltage to the wakeup circuit. In response to a wakeup switch being activated, the battery management device can provide a power supply (e.g., from a battery) to the power management device. Benefits of the wakeup circuit include (1) a reduction of battery consumption—and thus improving battery lifetime—when the electronic system is in a powered down mode of operation because the wakeup circuit has lower number of active components compared to other designs and (2) a non-complex wakeup circuit design because one or more existing connector interconnects between the power management device and the battery management device can be re-used during electronic system's powered down mode of operation.
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公开(公告)号：US11489533B2
公开(公告)日：2022-11-01
申请号：US16861103
申请日：2020-04-28
Applicant: Apple Inc.
Inventor： Bogdan-Eugen Matei , Hartmut Sturm
Abstract: An apparatus includes a power converter circuit configured to generate a voltage level on a regulated power supply node using a clock signal, and a clock generation circuit configured to dither a frequency of the clock signal. To transition from a first frequency to a second frequency, the clock generation circuit is configured to change, during an initial transition period, the clock signal between the first and second frequencies such that a particular percentage of clock pulses have the second frequency. During one or more intermediate transition periods, the clock generation circuit is configured to change the clock signal between the first and second frequencies such that a percentage of clock pulses having the second frequency increases relative to a prior transition period. During a final transition period of the series, the clock generation circuit is configured to set the frequency of the clock signal to the second frequency.
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公开(公告)号：US20210336626A1
公开(公告)日：2021-10-28
申请号：US16861103
申请日：2020-04-28
Applicant: Apple Inc.
Inventor： Bogdan-Eugen Matei , Hartmut Sturm
Abstract: An apparatus includes a power converter circuit configured to generate a voltage level on a regulated power supply node using a clock signal, and a clock generation circuit configured to dither a frequency of the clock signal. To transition from a first frequency to a second frequency, the clock generation circuit is configured to change, during an initial transition period, the clock signal between the first and second frequencies such that a particular percentage of clock pulses have the second frequency. During one or more intermediate transition periods, the clock generation circuit is configured to change the clock signal between the first and second frequencies such that a percentage of clock pulses having the second frequency increases relative to a prior transition period. During a final transition period of the series, the clock generation circuit is configured to set the frequency of the clock signal to the second frequency.
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