公开(公告)号：US12182926B1

公开(公告)日：2024-12-31

申请号：US18055111

申请日：2022-11-14

Applicant: Apple Inc.

Inventor： Jeffrey T. Brady ,  Jason D. Carroll ,  Michael A. Mang ,  Ralph C. Taylor

IPC: G06T15/00 ,  G06T17/20

Abstract: Techniques are disclosed relating to using an initial version of an object shader to determine a child count and distribute geometry work based on the child count. In some embodiments, graphics shader circuitry is configured to execute shader programs including object shaders and mesh shaders. Vertex control circuitry is configured to, for a given object shader: launch an initial version of the given object shader to determine a number of meshlets to be generated by the given object shader (e.g., where the initial version of the given object shader does not commit side effects to architectural state of the apparatus) and select shader circuitry to execute a complete version of the given object shader based on the determined number of meshlets.

公开(公告)号：US12169898B1

公开(公告)日：2024-12-17

申请号：US18054581

申请日：2022-11-11

Applicant: Apple Inc.

Inventor： Michael A. Mang ,  Jason D. Carroll ,  Jingfei Kong ,  Ralph C. Taylor

IPC: G06T17/20 ,  G06T15/00 ,  G06T15/20 ,  G06T15/40

Abstract: Techniques are disclosed relating to object and mesh shaders executed by a graphics processor. In some embodiments, a device includes buffer circuitry and shader circuitry configured to execute graphics programs. Control circuitry may: generate object shader work and mesh shader work for the shader circuitry, receive output information generated by a mesh shader that indicates a number of vertices and primitives to be output by the mesh shader, allocate, based on the output information and after execution of at least a portion of the mesh shader, a region of the buffer circuitry for storage of the vertices to be output by the mesh shader, and store the vertices output by the mesh shader in the allocated region. Disclosed techniques may advantageously provide efficient use of limited buffer resources.

公开(公告)号：US12165251B1

公开(公告)日：2024-12-10

申请号：US18054612

申请日：2022-11-11

Applicant: Apple Inc.

Inventor： Michael A. Mang ,  Jason D. Carroll ,  Jingfei Kong ,  Ralph C. Taylor

IPC: G06T15/00 ,  G06T1/60 ,  G06T15/10 ,  G06T17/20

Abstract: Techniques are disclosed relating to object and mesh shaders executed by a graphics processor. In some embodiments, a device includes buffer circuitry, shader circuitry configured to execute graphics programs, including mesh shaders that store output data in the buffer circuitry, and primitive processing circuitry configured to read data from buffer circuitry and process the data, including to cull primitives that are not visible in a graphics frame. Vertex control circuitry may receive: first signaling from the primitive processing circuitry that indicates whether the primitive processing circuitry is waiting for data from the buffer circuitry and second signaling from the shader circuitry that indicates whether the shader circuitry is blocked waiting for allocation in the buffer circuitry. The vertex control circuitry may adjust distribution of mesh shader work to the shader circuitry based on the first signaling and the second signaling.

公开(公告)号：US20250095268A1

公开(公告)日：2025-03-20

申请号：US18932992

申请日：2024-10-31

Applicant: Apple Inc.

Inventor： Michael A. Mang ,  Jason D. Carroll ,  Jingfei Kong ,  Ralph C. Taylor

IPC: G06T15/00 ,  G06T1/60 ,  G06T15/10 ,  G06T17/20

Abstract: Techniques are disclosed relating to object and mesh shaders executed by a graphics processor. In some embodiments, a device includes buffer circuitry, shader circuitry configured to execute graphics programs, including mesh shaders that store output data in the buffer circuitry, and primitive processing circuitry configured to read data from buffer circuitry and process the data, including to cull primitives that are not visible in a graphics frame. Vertex control circuitry may receive: first signaling from the primitive processing circuitry that indicates whether the primitive processing circuitry is waiting for data from the buffer circuitry and second signaling from the shader circuitry that indicates whether the shader circuitry is blocked waiting for allocation in the buffer circuitry. The vertex control circuitry may adjust distribution of mesh shader work to the shader circuitry based on the first signaling and the second signaling.

公开(公告)号：US10269091B1

公开(公告)日：2019-04-23

申请号：US15809687

申请日：2017-11-10

Applicant: Apple Inc.

Inventor： Michael A. Mang ,  Andrew M. Havlir

IPC: G06T1/20 ,  G06T15/00 ,  G06T1/60 ,  G06T7/49

Abstract: Techniques are disclosed relating to storage techniques for storing primitive information with vertex re-use. In some embodiments, graphics circuitry aggregates primitive information (including vertex data) for multiple primitives into a primitive block data structure. This may include storing only a single instance of a vertex for multiple primitives that share the vertex. The graphics circuitry may switch between primitive blocks, with one being active and the others non-active. For non-active primitive blocks, the graphics circuitry may track whether vertex identifiers have been used for a new vertex, which may prevent vertex re-use. If an identifier is not used for a new vertex, however, a vertex may be re-used across deactivation and reactivation of a primitive block.