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公开(公告)号：US12169898B1
公开(公告)日：2024-12-17
申请号：US18054581
申请日：2022-11-11
Applicant: Apple Inc.
Inventor： Michael A. Mang , Jason D. Carroll , Jingfei Kong , Ralph C. Taylor
Abstract: Techniques are disclosed relating to object and mesh shaders executed by a graphics processor. In some embodiments, a device includes buffer circuitry and shader circuitry configured to execute graphics programs. Control circuitry may: generate object shader work and mesh shader work for the shader circuitry, receive output information generated by a mesh shader that indicates a number of vertices and primitives to be output by the mesh shader, allocate, based on the output information and after execution of at least a portion of the mesh shader, a region of the buffer circuitry for storage of the vertices to be output by the mesh shader, and store the vertices output by the mesh shader in the allocated region. Disclosed techniques may advantageously provide efficient use of limited buffer resources.
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公开(公告)号：US20250095268A1
公开(公告)日：2025-03-20
申请号：US18932992
申请日：2024-10-31
Applicant: Apple Inc.
Inventor： Michael A. Mang , Jason D. Carroll , Jingfei Kong , Ralph C. Taylor
Abstract: Techniques are disclosed relating to object and mesh shaders executed by a graphics processor. In some embodiments, a device includes buffer circuitry, shader circuitry configured to execute graphics programs, including mesh shaders that store output data in the buffer circuitry, and primitive processing circuitry configured to read data from buffer circuitry and process the data, including to cull primitives that are not visible in a graphics frame. Vertex control circuitry may receive: first signaling from the primitive processing circuitry that indicates whether the primitive processing circuitry is waiting for data from the buffer circuitry and second signaling from the shader circuitry that indicates whether the shader circuitry is blocked waiting for allocation in the buffer circuitry. The vertex control circuitry may adjust distribution of mesh shader work to the shader circuitry based on the first signaling and the second signaling.
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公开(公告)号：US12165251B1
公开(公告)日：2024-12-10
申请号：US18054612
申请日：2022-11-11
Applicant: Apple Inc.
Inventor： Michael A. Mang , Jason D. Carroll , Jingfei Kong , Ralph C. Taylor
Abstract: Techniques are disclosed relating to object and mesh shaders executed by a graphics processor. In some embodiments, a device includes buffer circuitry, shader circuitry configured to execute graphics programs, including mesh shaders that store output data in the buffer circuitry, and primitive processing circuitry configured to read data from buffer circuitry and process the data, including to cull primitives that are not visible in a graphics frame. Vertex control circuitry may receive: first signaling from the primitive processing circuitry that indicates whether the primitive processing circuitry is waiting for data from the buffer circuitry and second signaling from the shader circuitry that indicates whether the shader circuitry is blocked waiting for allocation in the buffer circuitry. The vertex control circuitry may adjust distribution of mesh shader work to the shader circuitry based on the first signaling and the second signaling.
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