公开(公告)号：US12047088B2

公开(公告)日：2024-07-23

申请号：US17804920

申请日：2022-06-01

Applicant: Apple Inc.

Inventor： Jose V Santos Martinez ,  Yongxuan Hu ,  Nileshbhai J Shah

IPC: H03M1/12 ,  G06F5/06 ,  H03M1/00

CPC classification number: H03M1/1255 ,  G06F5/06 ,  H03M1/123 ,  H03M1/126 ,  H03M1/002 ,  H03M1/12 ,  H03M1/1265

Abstract: A data processing system can include a first IC including one or more A/D converters that receive analog inputs from one or more sensors and generate corresponding digital data, a second IC including one or more processing elements that operate on the digital data, and communication circuitry, coupled between the one or more A/D converters and processing elements, that includes a packetizer on the first IC that receives samples and sample data from the one or more A/D converters and assembles each sample and corresponding sample data into a packet, a primary physical interface on the first IC that communicates the packet to a secondary physical interface on the second IC, and a de-packetizer that on the second IC that receives the packet, de-packetizes it, and delivers the sample and sample data to the one or more processing elements.

公开(公告)号：US20230198538A1

公开(公告)日：2023-06-22

申请号：US17804920

申请日：2022-06-01

Applicant: Apple Inc.

Inventor： Jose V Santos Martinez ,  Yongxuan Hu ,  Nileshbhai J Shah

IPC: H03M1/12 ,  G06F5/06

CPC classification number: H03M1/1255 ,  H03M1/126 ,  H03M1/123 ,  G06F5/06

Abstract: A data processing system can include a first IC including one or more A/D converters that receive analog inputs from one or more sensors and generate corresponding digital data, a second IC including one or more processing elements that operate on the digital data, and communication circuitry, coupled between the one or more A/D converters and processing elements, that includes a packetizer on the first IC that receives samples and sample data from the one or more A/D converters and assembles each sample and corresponding sample data into a packet, a primary physical interface on the first IC that communicates the packet to a secondary physical interface on the second IC, and a de-packetizer that on the second IC that receives the packet, de-packetizes it, and delivers the sample and sample data to the one or more processing elements.