公开(公告)号：US20240143483A1

公开(公告)日：2024-05-02

申请号：US18406036

申请日：2024-01-05

Applicant: Apple Inc.

Inventor： Liran FISHEL ,  Danny GAL ,  Nir NISSAN

IPC: G06F11/36 ,  G06F9/30 ,  G06F9/32

CPC classification number: G06F11/3636 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30145 ,  G06F9/321 ,  G06F11/3656

Abstract: Embodiments of the present disclosure relate to debugging of an accelerator circuit using a packet limit breakpoint. A vector circuit reads a subset of instruction packets from an instruction memory and receives a portion of input data from a data memory corresponding to the subset of instruction packets. The vector circuit executes a set of vector operations in accordance with multiple instruction packets from the subset using data from the received portion of input data identified in the multiple instruction packets to generate output data. A program counter control circuit coupled to the instruction memory triggers a breakpoint in a program stored in the instruction memory causing the accelerator circuit to stop executing remaining instruction packets in the program following the multiple instruction packets responsive to a number of instruction packets executed in the program from a time instant of an event reaching a predetermined number.