公开(公告)号：US20240289250A1

公开(公告)日：2024-08-29

申请号：US18598003

申请日：2024-03-07

申请人： Supercell Oy

发明人： Aki Immonen

IPC分类号： G06F11/36 ,  G06F21/71

CPC分类号： G06F11/3612 ,  G06F11/3624 ,  G06F11/3656 ,  G06F21/71

摘要： A method for blocking external debugger application from analysing code of software program installed on computing device. The method including initializing software program including an application program and an internal debugger application. The software program, upon initialization thereof, instructs internal debugger application to load application program in internal debugger application. The internal debugger application is configured to utilize kernel resources of an operating system of the computing device. The method includes executing internal debugger application to set one or more break-points in code of application program to define execution path for code of application program, executing application program as per defined execution path for code thereof, stopping execution of code of application program upon reaching any of one or more break-points therein, and handing control to internal debugger application to provide an address for next instruction to be executed in defined execution path for code of application program.

公开(公告)号：US12072378B2

公开(公告)日：2024-08-27

申请号：US16707336

申请日：2019-12-09

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Tim Perley

IPC分类号： G01R31/3177 ,  G06F13/40 ,  G01R31/3185 ,  G06F11/07 ,  G06F11/26 ,  G06F11/36

CPC分类号： G01R31/3177 ,  G06F13/4027 ,  G01R31/3185 ,  G06F11/079 ,  G06F11/26 ,  G06F11/3656 ,  G06F11/3664

摘要： An integrated circuit (IC) includes a debug controller, a debug state machine (DSM), and an extended performance monitor counter (EPMC). The debug controller that selectively outputs debug data on a debug interconnect. The DSM identifies an event based on the debug data and an event list and outputs a DSM indication that identifies the event. The EPMC indicates a plurality of detected events including the identified event. The EPMC indicates the identified event in response to the DSM indication.

公开(公告)号：US20240241811A1

公开(公告)日：2024-07-18

申请号：US18155204

申请日：2023-01-17

申请人： STMicroelectronics International N.V.

发明人： Avneep Kumar GOYAL ,  Amritanshu ANAND ,  Satinder Singh MALHI

IPC分类号： G06F11/36 ,  G06F11/07 ,  G06F11/14

CPC分类号： G06F11/3656 ,  G06F11/0772 ,  G06F11/1441

摘要： In general, trace and debug logic should not be affected by all functional or destructive resets of a processing system. However, certain events, such as power supply related events may be utilized to reset the trace and debug logic since the trace and debug logic may cease correct operation if the provided power supply is insufficient. In addition, it may be beneficial for a debugger to initiate requests to reset trace and debug logic. Further, fault triggers from critical path monitors may be candidates as a source of reset for the trace and debug circuitry. For example, when critical path monitors trigger a fault, the fault may be from the logic associated with either trace and debug logic or the logic which is being debugged or traced. As such, in some instances both trace and debug circuitry and the processing system may be inoperable and may need to be reset.

公开(公告)号：US11977891B2

公开(公告)日：2024-05-07

申请号：US15012674

申请日：2016-02-01

申请人： Microsoft Technology Licensing, LLC

发明人： Douglas C. Burger ,  Aaron L. Smith

IPC分类号： G06F9/30 ,  G06F9/26 ,  G06F9/32 ,  G06F9/345 ,  G06F9/35 ,  G06F9/38 ,  G06F9/46 ,  G06F9/52 ,  G06F11/36 ,  G06F12/0806 ,  G06F12/0862 ,  G06F12/1009 ,  G06F13/42 ,  G06F15/78 ,  G06F15/80 ,  G06F9/355 ,  G06F12/0811 ,  G06F12/0875

CPC分类号： G06F9/3016 ,  G06F9/268 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/30138 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/32 ,  G06F9/345 ,  G06F9/35 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3848 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3856 ,  G06F9/38585 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/466 ,  G06F9/528 ,  G06F11/36 ,  G06F11/3648 ,  G06F11/3656 ,  G06F12/0806 ,  G06F12/0862 ,  G06F12/1009 ,  G06F13/4221 ,  G06F15/7867 ,  G06F15/80 ,  G06F15/8007 ,  G06F9/3013 ,  G06F9/321 ,  G06F9/355 ,  G06F9/3557 ,  G06F12/0811 ,  G06F12/0875 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/604 ,  G06F2212/62 ,  Y02D10/00

摘要： Apparatus and methods are disclosed for controlling execution of memory access instructions in a block-based processor architecture using a hardware structure that generates a relative ordering of memory access instruction in an instruction block. In one example of the disclosed technology, a method of executing an instruction block having a plurality of memory load and/or memory store instructions includes decoding an instruction block encoding a plurality of memory access instructions and generating data indicating a relative order for executing the memory access instructions in the instruction block and scheduling operation of a portion of the instruction block based at least in part on the relative order data. In some examples, a store vector data register can store the generated relative ordering data for use in subsequent instances of the instruction block.

公开(公告)号：US11968081B2

公开(公告)日：2024-04-23

申请号：US17579476

申请日：2022-01-19

申请人： Nile Global, Inc.

发明人： Promode Nedungadi ,  Sumanth Narayana Reddy ,  Ganesh Sathyanarayanan

IPC分类号： G06F11/07 ,  G06F11/36 ,  H04L41/0604 ,  H04L41/0631 ,  H04L41/0668 ,  G06F11/22 ,  H04L101/622

CPC分类号： H04L41/0668 ,  G06F11/3656 ,  H04L41/0627 ,  H04L41/065 ,  G06F11/0793 ,  G06F11/2294 ,  H04L2101/622

摘要： Embodiments of a device and method are disclosed. In an embodiment, a method for network device troubleshooting involves at a cloud server, connecting to a neighboring network device of a faulty network device, where the neighboring network device and the faulty network device are located within a network deployed at a customer site, and where the neighboring network device communicates with the faulty network device according to a short-range wireless communications protocol, and at the cloud server, performing a network device troubleshooting operation on the faulty network device using the neighboring network device as a proxy.

公开(公告)号：US20240077925A1

公开(公告)日：2024-03-07

申请号：US18505037

申请日：2023-11-08

申请人： Texas Instruments Incorporated

发明人： Jose Luis FLORES ,  Gary Augustine COOPER ,  Amritpal Singh MUNDRA ,  Anthony LELL ,  Jason Lynn PECK

IPC分类号： G06F1/3203 ,  G06F11/36

CPC分类号： G06F1/3203 ,  G06F11/3656

摘要： Circuits, systems and methods are provided. A circuit includes a subsystem, an interface, and a debugger. The interface includes power processing and management (PPM) circuitry coupled to the subsystem, and arbitration logic coupled to the PPM circuitry. In operation, the debugger issues a debug request to the arbitration logic to perform a debug operation on the subsystem, and, in response to the debug request, the arbitration logic provides an interrupt associated with the subsystem to the PPM circuitry. The PPM circuitry, in response to the interrupt and a determination that the subsystem is OFF, powers on the subsystem and provides a notification to the arbitration logic indicating that the subsystem is ON. The PPM circuitry also receives a notification from the arbitration logic that the debug operation related to the debug request is complete, and powers off the subsystem in response to that notification.

公开(公告)号：US20240070049A1

公开(公告)日：2024-02-29

申请号：US17895970

申请日：2022-08-25

申请人： Micron Technology, Inc.

发明人： Zhan Liu

IPC分类号： G06F11/36

CPC分类号： G06F11/3656 ,  G06F11/3636

摘要： In some aspects, the techniques described herein relate to a device including: a debug port; a trusted execution environment (TEE), the TEE storing a public key; and a controller, the controller configured to: receive a command to access the debug port, the command including a signature generated using a private key corresponding to the public key; provide the command to the TEE, wherein the TEE validates the command by validating the signature using the public key to obtain a validation result; and modify access to the debug port based on the validation result.

公开(公告)号：US11914716B2

公开(公告)日：2024-02-27

申请号：US17093576

申请日：2020-11-09

申请人： Lattice Semiconductor Corporation

发明人： Fulong Zhang ,  Srirama Chandra ,  Sreepada Hegade ,  Joel Coplen ,  Wei Han ,  Yu Sun

IPC分类号： G06F21/57 ,  G06F21/76 ,  H04L9/30 ,  H04L9/32 ,  G06F8/65 ,  G06F9/445 ,  G06F21/44 ,  G06F11/36 ,  G06F12/02 ,  G06F21/31 ,  G06F21/79 ,  G06F21/85 ,  H03K19/17768 ,  H04L9/08 ,  G06F21/10

CPC分类号： G06F21/575 ,  G06F8/65 ,  G06F9/44505 ,  G06F11/3656 ,  G06F12/0246 ,  G06F21/31 ,  G06F21/44 ,  G06F21/572 ,  G06F21/577 ,  G06F21/76 ,  G06F21/79 ,  G06F21/85 ,  H03K19/17768 ,  H04L9/085 ,  H04L9/0825 ,  H04L9/0877 ,  H04L9/30 ,  H04L9/3236 ,  H04L9/3252 ,  G06F21/107 ,  H04L2209/12

摘要： Systems and methods for asset management for secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD. The secure PLD is configured to receive a secure PLD asset access request from the PLD fabric or an external system coupled to the secure PLD through the configuration I/O, and to perform a secure PLD asset update process corresponding to the secure PLD asset access request, where the performing the asset update process is based on a lock status associated with a secure PLD asset corresponding to the secure PLD asset access request.

公开(公告)号：US11914500B2

公开(公告)日：2024-02-27

申请号：US17591888

申请日：2022-02-03

申请人： Apple Inc.

发明人： Liran Fishel ,  Danny Gal ,  Nir Nissan

IPC分类号： G06F9/48 ,  G06F11/36 ,  G06F11/00 ,  G06F9/44 ,  G06F9/46 ,  G06F9/32 ,  G06F9/30

CPC分类号： G06F11/3636 ,  G06F9/3004 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/321 ,  G06F11/3656

摘要： Embodiments of the present disclosure relate to debugging of an accelerator circuit using a packet limit breakpoint. A vector circuit reads a subset of instruction packets from an instruction memory and receives a portion of input data from a data memory corresponding to the subset of instruction packets. The vector circuit executes a set of vector operations in accordance with multiple instruction packets from the subset using data from the received portion of input data identified in the multiple instruction packets to generate output data. A program counter control circuit coupled to the instruction memory triggers a breakpoint in a program stored in the instruction memory causing the accelerator circuit to stop executing remaining instruction packets in the program following the multiple instruction packets responsive to a number of instruction packets executed in the program from a time instant of an event reaching a predetermined number.

公开(公告)号：US11907102B2

公开(公告)日：2024-02-20

申请号：US17582603

申请日：2022-01-24

申请人： Dell Products L.P.

发明人： Pravin Kumar A ,  Preeti Varma ,  Jayashree Radha

IPC分类号： G06F11/36

CPC分类号： G06F11/3656 ,  G06F11/366 ,  G06F11/3636

摘要： The present invention provides a system, computer readable code and method for dynamically performing debugging. The system, code, and method store debugging logs throughout an operation. At predetermined points the logs are stored to a cache. Older and/or unnecessary logs are periodically deleted from the cache to ensure that the cache does not grow to be larger than a predetermined size. This avoids the need to re-run a scenario after an error occurs in order to produce troubleshooting/debugging information.