公开(公告)号：US11496120B2

公开(公告)日：2022-11-08

申请号：US17150888

申请日：2021-01-15

Applicant: Apple Inc.

Inventor： Qi Ye ,  Ajay Bhatia ,  Vivekanandan Venugopal

IPC: H03K3/037 ,  H03K3/3562 ,  H03K3/356 ,  H03K3/012

Abstract: A flip-flop with glitch protection is disclosed. The flip-flop includes a differential amplifier circuit that generates amplifier output signals based on an input data and clock signals and precharges a true data node when a clock signal is inactive. A latch circuit is coupled to the differential amplifier and includes a latch node. Responsive to a current value of the input data signal having a first logic state, the latch node is set at a logic value equivalent to the precharged value during an active phase of the clock signal. Responsive to the current value of the input data signal having a second logic state complementary to the first, during the active phase of the clock signal, the latch circuit causes the latch node to be set to a logic value complementary to the precharged value, using the clock signal and the current value of the input data signal.

公开(公告)号：US20220231673A1

公开(公告)日：2022-07-21

申请号：US17150888

申请日：2021-01-15

Applicant: Apple Inc.

Inventor： Qi Ye ,  Ajay Bhatia ,  Vivekanandan Venugopal

IPC: H03K3/037 ,  H03K3/012 ,  H03K3/356 ,  H03K3/3562

Abstract: A flip-flop with glitch protection is disclosed. The flip-flop includes a differential amplifier circuit that generates amplifier output signals based on an input data and clock signals and precharges a true data node when a clock signal is inactive. A latch circuit is coupled to the differential amplifier and includes a latch node. Responsive to a current value of the input data signal having a first logic state, the latch node is set at a logic value equivalent to the precharged value during an active phase of the clock signal. Responsive to the current value of the input data signal having a second logic state complementary to the first, during the active phase of the clock signal, the latch circuit causes the latch node to be set to a logic value complementary to the precharged value, using the clock signal and the current value of the input data signal.

公开(公告)号：US20220094340A1

公开(公告)日：2022-03-24

申请号：US17028790

申请日：2020-09-22

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Qi Ye

IPC: H03K3/037

Abstract: Systems, apparatuses, and methods for implementing a low-power, single-pin retention flip-flop with a balloon latch are described. A flip-flop is connected to a retention latch to store a value of the flip-flop during a reduced power state. A single retention pin is used to turn on the retention latch. During normal mode, the retention latch is pre-charged and a change in the value stored by the flip-flop does not cause the retention latch to toggle. This helps to reduce the power consumed by the circuit during normal mode (i.e., non-retention mode). When the retention signal becomes active, the retention latch gets triggered and the value stored by the flip-flop is written into the retention latch. Later, if the flip-flop is powered down and then powered back up while the circuit is in retention mode, the value in the retention latch gets written back into the flip-flop.

公开(公告)号：US20210344329A1

公开(公告)日：2021-11-04

申请号：US17327365

申请日：2021-05-21

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Ajay Bhatia ,  Qi Ye

IPC: H03K3/012 ,  H03K3/037

Abstract: Systems, apparatuses, and methods for implementing low voltage clock swing sequential circuits are described. An input signal is coupled to the gates of a first P-type transistor and a first N-type transistor of a first transistor stack. A low voltage swing clock signal is coupled to the gate of a second N-type transistor of the first transistor stack. An inverse of the input signal is coupled to the gates of a second P-type transistor and a third N-type transistor of a second transistor stack. The low-swing clock is coupled to the gate of a fourth N-type transistor of the second transistor stack. A first end of one or more enabling P-Type transistors with gates coupled to the low-swing clock is coupled to the first P-type transistor's drain, and a second end of the one or more enabling P-Type transistors is coupled to the second P-type transistor's drain.

公开(公告)号：US11424734B2

公开(公告)日：2022-08-23

申请号：US17327365

申请日：2021-05-21

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Ajay Bhatia ,  Qi Ye

IPC: H03K3/012 ,  H03K3/037

Abstract: Systems, apparatuses, and methods for implementing low voltage clock swing sequential circuits are described. An input signal is coupled to the gates of a first P-type transistor and a first N-type transistor of a first transistor stack. A low voltage swing clock signal is coupled to the gate of a second N-type transistor of the first transistor stack. An inverse of the input signal is coupled to the gates of a second P-type transistor and a third N-type transistor of a second transistor stack. The low-swing clock is coupled to the gate of a fourth N-type transistor of the second transistor stack. A first end of one or more enabling P-Type transistors with gates coupled to the low-swing clock is coupled to the first P-type transistor's drain, and a second end of the one or more enabling P-Type transistors is coupled to the second P-type transistor's drain.

公开(公告)号：US11336272B2

公开(公告)日：2022-05-17

申请号：US17028790

申请日：2020-09-22

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Qi Ye

IPC: H03K3/012 ,  H03K3/356 ,  H03K3/037 ,  H03K3/0233

Abstract: Systems, apparatuses, and methods for implementing a low-power, single-pin retention flip-flop with a balloon latch are described. A flip-flop is connected to a retention latch to store a value of the flip-flop during a reduced power state. A single retention pin is used to turn on the retention latch. During normal mode, the retention latch is pre-charged and a change in the value stored by the flip-flop does not cause the retention latch to toggle. This helps to reduce the power consumed by the circuit during normal mode (i.e., non-retention mode). When the retention signal becomes active, the retention latch gets triggered and the value stored by the flip-flop is written into the retention latch. Later, if the flip-flop is powered down and then powered back up while the circuit is in retention mode, the value in the retention latch gets written back into the flip-flop.

公开(公告)号：US11018653B1

公开(公告)日：2021-05-25

申请号：US16866307

申请日：2020-05-04

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Ajay Bhatia ,  Qi Ye

IPC: H03K3/012 ,  H03K3/037

Abstract: Systems, apparatuses, and methods for implementing low voltage clock swing sequential circuits are described. An input signal is coupled to the gates of a first P-type transistor and a first N-type transistor of a first transistor stack. A low voltage swing clock signal is coupled to the gate of a second N-type transistor of the first transistor stack. An inverse of the input signal is coupled to the gates of a second P-type transistor and a third N-type transistor of a second transistor stack. The low-swing clock is coupled to the gate of a fourth N-type transistor of the second transistor stack. A first end of one or more enabling P-Type transistors with gates coupled to the low-swing clock is coupled to the first P-type transistor's drain, and a second end of the one or more enabling P-Type transistors is coupled to the second P-type transistor's drain.