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公开(公告)号：US11914973B2
公开(公告)日：2024-02-27
申请号：US16953093
申请日：2020-11-19
Applicant: Apple Inc.
Inventor： Shahzad Nazar , Bharan Giridhar , Mohamed H. Abu-Rahma , Ajay Bhatia , Mayur V. Joshi , Yildiz Sinangil , Aravind Kandala
CPC classification number: G06F7/5443 , G06F7/523 , G06F17/15 , H03M1/46 , G06N20/00
Abstract: A compute-memory circuit included in a computer system includes multiple data storage cells and multiplier circuits. The data storage cells store weight values associated with a first operand. The multiplier circuits are coupled to a global bit line and receive the weight values via local bit lines coupled to the data storage cells. Using the received weight values and activation signals indicative of a second operand, the multiplier circuits modify a voltage level of the global bit line. The resultant voltage level on the global bit line is indicative of a product of the first and second operands, and can be converted to a digital value using an analog-to-digital converter circuit.
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公开(公告)号：US11496120B2
公开(公告)日：2022-11-08
申请号：US17150888
申请日：2021-01-15
Applicant: Apple Inc.
Inventor： Qi Ye , Ajay Bhatia , Vivekanandan Venugopal
IPC: H03K3/037 , H03K3/3562 , H03K3/356 , H03K3/012
Abstract: A flip-flop with glitch protection is disclosed. The flip-flop includes a differential amplifier circuit that generates amplifier output signals based on an input data and clock signals and precharges a true data node when a clock signal is inactive. A latch circuit is coupled to the differential amplifier and includes a latch node. Responsive to a current value of the input data signal having a first logic state, the latch node is set at a logic value equivalent to the precharged value during an active phase of the clock signal. Responsive to the current value of the input data signal having a second logic state complementary to the first, during the active phase of the clock signal, the latch circuit causes the latch node to be set to a logic value complementary to the precharged value, using the clock signal and the current value of the input data signal.
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公开(公告)号：US20200313660A1
公开(公告)日：2020-10-01
申请号：US16804675
申请日：2020-02-28
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Ajay Bhatia , Wenhao Li
IPC: H03K3/037 , H03K19/0185
Abstract: Techniques are disclosed relating to level-shifting circuitry and time borrowing across voltage domains. In disclosed embodiments, an apparatus includes pulse circuitry, latch circuitry, pull circuitry, and feedback circuitry. The pulse circuitry is configured to generate a pulse signal in response to an active clock edge. The latch circuitry is configured to store a value of an input signal, where the input signal has a first voltage level. The pull circuitry is configured to drive, during the pulse signal, an output of the latch circuitry to match a logical value of the input signal at a second, different voltage level. This may allow the input signal to change during the pulse, enabling time borrowing. The feedback circuitry is configured to maintain the output of the latch circuitry at the second voltage level after the pulse signal.
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公开(公告)号：US20240231758A1
公开(公告)日：2024-07-11
申请号：US18417868
申请日：2024-01-19
Applicant: Apple Inc.
Inventor： Shahzad Nazar , Bharan Giridhar , Mohamed H. Abu-Rahma , Ajay Bhatia , Mayur V. Joshi , Yildiz Sinangil , Aravind Kandala
CPC classification number: G06F7/5443 , G06F7/523 , G06F17/15 , H03M1/46 , G06N20/00
Abstract: A compute-memory circuit included in a computer system includes multiple data storage cells and multiplier circuits. The data storage cells store weight values associated with a first operand. The multiplier circuits are coupled to a global bit line and receive the weight values via local bit lines coupled to the data storage cells. Using the received weight values and activation signals indicative of a second operand, the multiplier circuits modify a voltage level of global bit line. The resultant voltage level on the global bit line is indicative of a product of the first and second operands, and can be converted to a digital value using an analog-to-digital converter circuit. By performing computation on global rather than local bit lines, standard data storage cells can be employed, improving the area efficiency of the compute-memory circuit.
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公开(公告)号：US20230298996A1
公开(公告)日：2023-09-21
申请号：US17655699
申请日：2022-03-21
Applicant: Apple Inc.
Inventor： Mohamed H. Abu-Rahma , Antonietta Oliva , Ajay Bhatia , Shahzad Nazar
IPC: H01L23/528 , H01L27/11
CPC classification number: H01L23/528 , H01L27/1104 , H01L27/1116
Abstract: Various implementations of backside and topside routing of bitlines and wordlines in memory arrays are disclosed. Bitlines in backside and topside metal layers may be alternated between adjacent bit cells in a memory array. Alternating the location of the bitlines between bit cells in the memory array may reduce bitline capacitance in a memory array. Placing wordlines in backside metal layers may allow dual wordlines to be implemented across a span of bit cells in a memory array. The dual wordlines may be alternately connected to adjacent bit cells, thereby allowing selective toggling of bit cells based on the wordline transmitting a control signal.
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Patent Agency Ranking
公开(公告)号：US20220101914A1
公开(公告)日：2022-03-31
申请号：US17317844
申请日：2021-05-11
Applicant: Apple Inc.
Inventor： Michael A. Dreesen , Ajay Bhatia , Michael R. Seningen , Greg M. Hess , Siddhesh Gaiki
IPC: G11C11/412 , G11C11/419 , G06F7/523
Abstract: A compute-memory circuit included in a computer system may include multiple compute data storage cells coupled to a compute bit line via respective capacitors. The compute data storage cells may store respective bits of a weight value. During a multiply operation, an operand may be used to generate a voltage level on a compute word line that is used to store respective amounts of charge on the capacitors, which are coupled to the compute bit line. The voltage on the compute bit line may be converted into multiple bits whose value is indicative of a product of the operand and the weight value.
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公开(公告)号：US20210344329A1
公开(公告)日：2021-11-04
申请号：US17327365
申请日：2021-05-21
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Ajay Bhatia , Qi Ye
Abstract: Systems, apparatuses, and methods for implementing low voltage clock swing sequential circuits are described. An input signal is coupled to the gates of a first P-type transistor and a first N-type transistor of a first transistor stack. A low voltage swing clock signal is coupled to the gate of a second N-type transistor of the first transistor stack. An inverse of the input signal is coupled to the gates of a second P-type transistor and a third N-type transistor of a second transistor stack. The low-swing clock is coupled to the gate of a fourth N-type transistor of the second transistor stack. A first end of one or more enabling P-Type transistors with gates coupled to the low-swing clock is coupled to the first P-type transistor's drain, and a second end of the one or more enabling P-Type transistors is coupled to the second P-type transistor's drain.
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公开(公告)号：US10734040B1
公开(公告)日：2020-08-04
申请号：US16369395
申请日：2019-03-29
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Ajay Bhatia
Abstract: Techniques are disclosed relating to level-shifting circuitry and time borrowing across voltage domains. In some embodiments, sense amplifier circuitry generates, based on an input signal at a first voltage level, an output signal at a second, different voltage level. Pulse circuitry may generate a pulse signal in response to an active clock edge of a clock signal that is input to the sense amplifier circuitry. Initial resolution circuitry may drive the output signal of the sense amplifier circuitry to match the value of the input signal during the pulse signal. Secondary resolution circuitry may maintain a current value of the output signal after expiration of the pulse signal. This may allow the input signal to change during the pulse, e.g., to enable time borrowing by upstream circuitry.
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公开(公告)号：US20190089354A1
公开(公告)日：2019-03-21
申请号：US15710406
申请日：2017-09-20
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Michael R. Seningen , Ajay Bhatia
Abstract: A clock gating circuit is disclosed. The clock gating circuit includes an input circuit configured to receive an enable signal and clock enable circuitry configured to receive an input clock signal. The clock gating circuit also includes a latch that captures and stores an enabled state of the enable signal when the enable signal is asserted. An output circuit is coupled to the latch, and provides an output signal corresponding to a state of the clock signal when the latch is storing the enabled state. The clock gating circuit is arranged such that, when the latch is not storing the enabled state, no dynamic power is consumed responsive to state changes of the input clock signal.
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公开(公告)号：US20190089337A1
公开(公告)日：2019-03-21
申请号：US15710526
申请日：2017-09-20
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Michael R Seningen , Ajay Bhatia
IPC: H03K3/037
Abstract: An electronic circuit is disclosed. A first flip-flop is coupled to receive a clock signal from clock gating circuit. The first flip-flop includes an input circuit having a data input, a master-slave latch, and an output circuit. Responsive to an edge of the clock signal, the master-slave latch may latch a logic value of a signal received on the data input. The output circuit is coupled to the master-slave latch, and provides a logic output signal corresponding to the logic value latched by the master-slave latch. The clock gating circuit may provide one or more inversions of the clock signal which it receives. The flip-flop provides no inversions of the clock signal.
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