公开(公告)号：US20220101914A1

公开(公告)日：2022-03-31

申请号：US17317844

申请日：2021-05-11

Applicant: Apple Inc.

Inventor： Michael A. Dreesen ,  Ajay Bhatia ,  Michael R. Seningen ,  Greg M. Hess ,  Siddhesh Gaiki

IPC: G11C11/412 ,  G11C11/419 ,  G06F7/523

Abstract: A compute-memory circuit included in a computer system may include multiple compute data storage cells coupled to a compute bit line via respective capacitors. The compute data storage cells may store respective bits of a weight value. During a multiply operation, an operand may be used to generate a voltage level on a compute word line that is used to store respective amounts of charge on the capacitors, which are coupled to the compute bit line. The voltage on the compute bit line may be converted into multiple bits whose value is indicative of a product of the operand and the weight value.