公开(公告)号：US20230342298A1

公开(公告)日：2023-10-26

申请号：US17729233

申请日：2022-04-26

Applicant: Arm Limited

Inventor： Vladimir VASEKIN ,  David Michael BULL ,  Vincent REZARD ,  Anton ANTONOV

IPC: G06F12/0842 ,  G06F12/0891 ,  G06F9/38

CPC classification number: G06F12/0842 ,  G06F12/0891 ,  G06F9/3816 ,  G06F2212/1021

Abstract: Apparatus, method and code for fabrication of the apparatus, the apparatus comprising a cache providing a plurality of cache lines, each cache line storing a block of data; cache access control circuitry, responsive to an access request, to determine whether a hit condition is present in the cache; and cache configuration control circuitry to set, in response to a merging trigger event, merge indication state identifying multiple cache lines to be treated as a merged cache line to store multiple blocks of data, wherein when the merge indication state indicates that the given cache line is part of the merged cache line, the cache access control circuitry is responsive to detecting the hit condition to allow access to any of the data blocks stored in the multiple cache lines forming the merged cache line.