公开(公告)号：US20240220411A1

公开(公告)日：2024-07-04

申请号：US18405944

申请日：2024-01-05

Applicant: FLC Technology Group, Inc.

Inventor： Sehat Sutardja

IPC: G06F12/0811 ,  G06F9/38 ,  G06F9/50 ,  G06F12/0846 ,  G06F12/1009 ,  G06F12/0897

CPC classification number: G06F12/0811 ,  G06F9/3816 ,  G06F9/5077 ,  G06F12/0851 ,  G06F12/1009 ,  G06F12/0897

Abstract: A data access system including a processor, multiple cache modules for the main memory, and a storage drive. The cache modules include a FLC controller and a main memory cache. The multiple cache modules function as main memory. The processor sends read/write requests (with physical address) to the cache module. The cache module includes two or more stages with each stage including a FLC controller and DRAM (with associated controller). If the first stage FLC module does not include the physical address, the request is forwarded to a second stage FLC module. If the second stage FLC module does not include the physical address, the request is forwarded to the storage drive, a partition reserved for main memory. The first stage FLC module has high speed, lower power operation while the second stage FLC is a low-cost implementation. Multiple FLC modules may connect to the processor in parallel.

公开(公告)号：US12001282B2

公开(公告)日：2024-06-04

申请号：US17956136

申请日：2022-09-29

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet Ashok Chachad ,  Timothy David Anderson ,  David Matthew Thompson ,  Daniel Brad Wu

IPC: G06F11/10 ,  G06F3/06 ,  G06F9/38 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/12 ,  G06F12/126 ,  H04W24/10 ,  H04W56/00 ,  H04W72/02 ,  H04W72/044 ,  H04W74/08 ,  H04W74/0833

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0685 ,  G06F9/3816 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/126 ,  H04W24/10 ,  H04W56/001 ,  H04W72/02 ,  H04W72/044 ,  H04W74/0841 ,  H04W74/0866 ,  G06F3/0604 ,  G06F2212/608

Abstract: In described examples, a processor system includes a processor core that generates memory write requests, and a cache memory with a memory controller having a memory pipeline. The cache memory has cache lines of length L. The cache memory has a minimum write length that is less than a cache line length of the cache memory. The memory pipeline determines whether the data payload includes a first chunk and ECC syndrome that correspond to a partial write and are writable by a first cache write operation, and a second chunk and ECC syndrome that correspond to a full write operation that can be performed separately from the first cache write operation. The memory pipeline performs an RMW operation to store the first chunk and ECC syndrome in the cache memory, and performs the full write operation to store the second chunk and ECC syndrome in the cache memory.

公开(公告)号：US11915004B2

公开(公告)日：2024-02-27

申请号：US17556166

申请日：2021-12-20

Applicant: Arm Limited

Inventor： Houdhaifa Bouzguarrou ,  Thibaut Elie Lanois ,  Guillaume Bolbenes

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3844 ,  G06F9/30054 ,  G06F9/3816

Abstract: A data processing apparatus is provided that includes bimodal control flow prediction circuitry for performing a prediction of whether a conditional control flow instruction will be taken. Storage circuitry stores, in association with the control flow instruction, a stored state of the data processing apparatus and reversal circuitry reverses the prediction in dependence on the stored state of the data processing apparatus corresponding with a current state of the data processing apparatus when execution of the control flow instruction is to be performed.

公开(公告)号：US11880305B2

公开(公告)日：2024-01-23

申请号：US18094228

申请日：2023-01-06

Applicant: FLC Technology Group, Inc.

Inventor： Sehat Sutardja

IPC: G06F12/0811 ,  G06F12/0846 ,  G06F9/50 ,  G06F9/38 ,  G06F12/1009 ,  G06F12/0897

CPC classification number: G06F12/0811 ,  G06F9/3816 ,  G06F9/5077 ,  G06F12/0851 ,  G06F12/1009 ,  G06F12/0897

Abstract: A data access system including a processor, multiple cache modules for the main memory, and a storage drive. The cache modules include a FLC controller and a main memory cache. The multiple cache modules function as main memory. The processor sends read/write requests (with physical address) to the cache module. The cache module includes two or more stages with each stage including a FLC controller and DRAM (with associated controller). If the first stage FLC module does not include the physical address, the request is forwarded to a second stage FLC module. If the second stage FLC module does not include the physical address, the request is forwarded to the storage drive, a partition reserved for main memory. The first stage FLC module has high speed, lower power operation while the second stage FLC is a low-cost implementation. Multiple FLC modules may connect to the processor in parallel.

公开(公告)号：US20230315644A1

公开(公告)日：2023-10-05

申请号：US17708785

申请日：2022-03-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： ROBERT J. SONNELITTER, III ,  EKATERINA M. AMBROLADZE ,  TIMOTHY BRONSON ,  MICHAEL A. BLAKE ,  TU-AN T. NGUYEN

IPC: G06F12/0891 ,  G06F12/0811 ,  G06F12/0817 ,  G06F9/38

CPC classification number: G06F12/0891 ,  G06F12/0811 ,  G06F12/0824 ,  G06F9/3816

Abstract: Castout handling in a distributed cache topology, including: detecting, by a first cache of a plurality of caches, a cache miss; providing, by the first cache to each other cache of the plurality of caches, a message comprising: data indicating a cache address corresponding to the cache miss; and data indicating a cache line to be evicted.

公开(公告)号：US10001993B2

公开(公告)日：2018-06-19

申请号：US14457929

申请日：2014-08-12

Applicant: Linear Algebra Technologies Limited

Inventor： Brendan Barry ,  Fergal Connor ,  Martin O'Riordan ,  David Moloney ,  Sean Power

IPC: G06F9/30 ,  G06F1/32 ,  G06F9/38 ,  G06F15/80

CPC classification number: G06F9/30036 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/30 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30149 ,  G06F9/3804 ,  G06F9/3816 ,  G06F9/3822 ,  G06F15/8053 ,  Y02D10/152 ,  Y02D10/171

Abstract: A vector processor is disclosed including a variety of variable-length instructions. Computer-implemented methods are disclosed for efficiently carrying out a variety of operations in a time-conscious, memory-efficient, and power-efficient manner. Methods for more efficiently managing a buffer by controlling the threshold based on the length of delay line instructions are disclosed. Methods for disposing multi-type and multi-size operations in hardware are disclosed. Methods for condensing look-up tables are disclosed. Methods for in-line alteration of variables are disclosed.

公开(公告)号：US20180165096A1

公开(公告)日：2018-06-14

申请号：US15374727

申请日：2016-12-09

Applicant: Advanced Micro Devices, Inc.

Inventor： David N. Suggs

IPC: G06F9/38 ,  G06F12/0875

CPC classification number: G06F9/3808 ,  G06F9/3012 ,  G06F9/30152 ,  G06F9/30167 ,  G06F9/30174 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3816 ,  G06F9/382 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3846 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3885 ,  G06F9/3891 ,  G06F12/0855 ,  G06F12/0862 ,  G06F12/0875 ,  G06F2212/1024 ,  G06F2212/452 ,  G06F2212/6028

Abstract: A system and method for using an operation (op) cache is disclosed. The system and method include an op cache for caching previously decoded instructions. The op cache includes a plurality of physically indexed and tagged instructions allowing sharing of instructions between threads. The op cache is chained through multiple ways allowing service of a plurality of instructions in a cache line. The op cache is stored between a shared operation storage and immediate/displacement storage to maximize capacity.

公开(公告)号：US20170177370A1

公开(公告)日：2017-06-22

申请号：US15448280

申请日：2017-03-02

Applicant: FUJITSU LIMITED ,  FUJITSU SEMICONDUCTOR LIMITED

Inventor： Mitsuru Tomono ,  Hiroya Uehara ,  Makiko Ito

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30185 ,  G06F9/30032 ,  G06F9/30072 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30178 ,  G06F9/3802 ,  G06F9/3816

Abstract: A processor accesses memory storing a compressed instruction sequence that includes compression information indicating that an instruction that with respect to the preceding instruction, has identical operation code and operand continuity is compressed. The processor includes a fetcher that fetches a bit string from the memory and determines whether the bit string is a non-compressed instruction, where if so, transfers the given bit string and if not, transfers the compression information; and a decoder that upon receiving the non-compressed instruction, holds in a buffer, instruction code and an operand pattern of the non-compressed instruction and executes processing to set to an initial value, the value of an instruction counter that indicates a count of consecutive instructions having identical operation code and operand continuity, and upon receiving the compression information, restores the instruction code based on the instruction code held in the buffer, the instruction counter value, and the operand pattern.

公开(公告)号：US20160070575A1

公开(公告)日：2016-03-10

申请号：US14939932

申请日：2015-11-12

Applicant: INTEL CORPORATION

Inventor： Julien Sebot ,  William W. Macy, JR. ,  Eric L. Debes ,  Huy V. Nguyen

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/3816 ,  G06F9/3885 ,  G06F15/8007 ,  G06F17/147 ,  G06F17/15

Abstract: Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.

公开(公告)号：US09182988B2

公开(公告)日：2015-11-10

申请号：US13788899

申请日：2013-03-07

Applicant: Intel Corporation

Inventor： Yen-Kuang Chen ,  William W. Macy, Jr. ,  Matthew Holliman ,  Eric L. Debes ,  Minerva M. Yeung ,  Huy V. Nguyen ,  Julien Sebot

IPC: G06F5/01 ,  G06F9/30 ,  G06F9/38 ,  G06F17/14 ,  G06F17/15 ,  G06F15/80

CPC classification number: G06F9/30145 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/3816 ,  G06F9/3885 ,  G06F15/8007 ,  G06F17/147 ,  G06F17/15

Abstract: Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.