公开(公告)号：US20200004551A1

公开(公告)日：2020-01-02

申请号：US16025116

申请日：2018-07-02

Applicant: Arm Limited

Inventor： Vladimir VASEKIN ,  David Michael BULL ,  Alexei FEDOROV

IPC: G06F9/38

Abstract: An apparatus and method are provided for using predicted result values. The apparatus has processing circuitry for executing a sequence of instructions, and value prediction storage that comprises a plurality of entries, where each entry is used to identify a predicted result value for an instruction allocated to that entry. Dispatch circuitry maintains a record of pending instructions awaiting execution by the processing circuitry, and selects pending instructions from the record for dispatch to the processing circuitry for execution. The dispatch circuitry is arranged to enable at least one pending instruction to be speculatively executed by the processing circuitry using as a source operand a predicted result value provided by the value prediction storage. Allocation circuitry is arranged to apply a default allocation policy to identify a first instruction to be allocated an entry in the value prediction storage. However, the allocation circuitry is further responsive to a trigger condition to identify a dependent instruction whose result value will be dependent on the result value produced by executing the first instruction, and to then allocate an entry in the value prediction storage to store a predicted result value for the identified dependent instruction. Such an approach can enable performance improvements to be achieved through the use of predicted result values even in situations where the prediction accuracy of the predicted result value for the first instruction proves not to be that high, by instead enabling a predicted result value for the dependent instruction to be used to allow speculative execution of further dependent instructions.

公开(公告)号：US20190196832A1

公开(公告)日：2019-06-27

申请号：US15855139

申请日：2017-12-27

Applicant: Arm Limited

Inventor： Vladimir VASEKIN ,  Chiloda Ashan Senarath PATHIRANE ,  Jungsoo KIM ,  Alexei FEDOROV

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30196 ,  G06F9/3802 ,  G06F9/3867

Abstract: A data processing system 2 includes an instruction pipeline 14 containing instruction queue circuitry 28, fusion circuitry 30 and decoder circuitry 32. The fusion circuitry 30 serves to identify fusible groups of program instructions within a Y-wide window of program instructions and supply a stream of program instructions including such replacement fused program instructions to a X-wide decoder circuitry 32 which decodes X program instructions in parallel using parallel decoders 40, 42, 44.

公开(公告)号：US20170199738A1

公开(公告)日：2017-07-13

申请号：US14989841

申请日：2016-01-07

Applicant: ARM LIMITED

Inventor： Vladimir VASEKIN ,  Antony John PENTON ,  Chiloda Ashan Senarath PATHIRANE ,  Andrew James Antony LEES

IPC: G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/384 ,  G06F9/3851

Abstract: Data processing circuitry comprises allocation circuitry to allocate one or more source and destination processor registers, of a set of processor registers each defined by a respective register index, to a processor instruction for use in execution of that processor instruction and to associate, with the processor instruction, information to indicate the register index of the allocated source and destination processor registers; the avocation circuitry being selectively operable to allocate, to a processor instruction, a group of destination processor registers having a subset of their register indices in common and to associate, with the processor instruction, information to indicate the register index of one processor register of the group and identifying information to identify one or more bits of the register index which differ between the processor registers in the allocated group of processor registers.

公开(公告)号：US20140122846A1

公开(公告)日：2014-05-01

申请号：US13664659

申请日：2012-10-31

Applicant: ARM LIMITED

Inventor： Vladimir VASEKIN ,  Allan John SKILLMAN ,  Chiloda Ashan Senerath PATHIRANE ,  Jean-Baptiste BRELOT

IPC: G06F9/38

CPC classification number: G06F9/3806

Abstract: An integrated circuit 2 incorporates prefetch circuitry 12 for prefetching program instructions from a memory 6. The prefetch circuitry 12 includes a branch target address cache 28. The branch target address cache 28 stores data indicative of branch target addresses of previously encountered branch instructions fetched from the memory 6. For each previously encountered branch instructions, the branch target address cache stores a tag value indicative of a fetch address of that previously encountered branch instruction. The tag values stored are generated by tag value generating circuitry 32 which performs a hashing function upon a portion of the fetch address such that the tag value has a bit length less than the bit length of the portion of the fetch address concerned.

Abstract translation: 集成电路2包含用于从存储器6预取程序指令的预取电路12.预取电路12包括分支目标地址高速缓存28.分支目标地址高速缓存28存储指示从先前遇到的分支指令的分支目标地址 对于每个先前遇到的分支指令，分支目标地址高速缓存存储指示先前遇到的分支指令的获取地址的标签值。 存储的标签值由标签值生成电路32产生，标签值生成电路32对获取地址的一部分执行散列函数，使得标签值的位长度小于相关提取地址的位长度。

公开(公告)号：US20200004547A1

公开(公告)日：2020-01-02

申请号：US16021178

申请日：2018-06-28

Applicant: Arm Limited

Inventor： Vladimir VASEKIN ,  David Michael BULL ,  Chiloda Ashan Senarath PATHIRANE ,  Alexei FEDOROV

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/54 ,  G06F21/64

Abstract: An apparatus and method are provided for using predicted result values. The apparatus has a processing unit that comprises processing circuitry for executing a sequence of instructions, and value prediction circuitry for identifying a predicted result value for at least one instruction. A result producing structure is provided that is responsive to a request issued from the processing unit when the processing circuitry is executing a first instruction, to produce a result value for the first instruction and return that result value to the processing unit. While waiting for the result value from the result producing structure, the processing circuitry can be arranged to speculatively execute at least one dependent instruction using a predicted result value for the first instruction as obtained from the value prediction circuitry. The request issued from the processing unit includes a signature value indicative of the predicted result value, and the result producing structure references the signature value in order to detect whether a mispredict condition exists indicating that the predicted result value differs from the result value. The apparatus further provides a mispredict signal transmission path via which the result producing structure, when the mispredict condition is detected, can assert a mispredict signal for receipt by the processing unit prior to the result value being available to the processing unit. Such an approach can reduce the misprediction penalty associated with using a mispredicted result value.

公开(公告)号：US20180088951A1

公开(公告)日：2018-03-29

申请号：US15571915

申请日：2016-04-11

Applicant: Arm Limited

Inventor： Antony John PENTON ,  Simon John CRASKE ,  Vladimir VASEKIN

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30123 ,  G06F9/3005 ,  G06F9/30076 ,  G06F9/30189 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3863 ,  G06F9/3889

Abstract: Apparatus for processing data (2) includes issue circuitry (22) for issuing program instructions (processing operations) to execute either within real time execution circuitry (32) or non real time execution circuitry (24, 26, 28, 30). Registers within a register file (18) are marked as non real time dependent registers if they are allocated to store a data value which is to be written by an uncompleted program instruction issued to the non real time execution circuitry and not yet completed. Issue policy control circuitry (42) responds to a trigger event to enter a real time issue policy mode to control the issue circuitry (22) to issue candidate processing operations (such as program instruction, micro-operations, architecturally triggered processing operations etc.) to one of the non real time execution circuitry or the real time execution circuitry in dependence upon whether that candidate processing operation reads a register marked as a non real time dependent register.

公开(公告)号：US20250004945A1

公开(公告)日：2025-01-02

申请号：US18343971

申请日：2023-06-29

Applicant: Arm Limited

Inventor： Vladimir VASEKIN ,  Vincent REZARD ,  Antony John PENTON ,  Cédric Denis Robert AIRAUD

IPC: G06F12/0862

Abstract: An apparatus comprises associating circuitry to associate an indirect prefetch condition with a memory access request when hint information indicates that the data to be accessed in response to the memory access request is address indicating data which is to be used to generate a second address for a subsequent memory access request. A second address can be generated using the address indicating data, and a prefetch memory access request can be issued to seek to make data at the second address available in the associated cache.

公开(公告)号：US20230342298A1

公开(公告)日：2023-10-26

申请号：US17729233

申请日：2022-04-26

Applicant: Arm Limited

Inventor： Vladimir VASEKIN ,  David Michael BULL ,  Vincent REZARD ,  Anton ANTONOV

IPC: G06F12/0842 ,  G06F12/0891 ,  G06F9/38

CPC classification number: G06F12/0842 ,  G06F12/0891 ,  G06F9/3816 ,  G06F2212/1021

Abstract: Apparatus, method and code for fabrication of the apparatus, the apparatus comprising a cache providing a plurality of cache lines, each cache line storing a block of data; cache access control circuitry, responsive to an access request, to determine whether a hit condition is present in the cache; and cache configuration control circuitry to set, in response to a merging trigger event, merge indication state identifying multiple cache lines to be treated as a merged cache line to store multiple blocks of data, wherein when the merge indication state indicates that the given cache line is part of the merged cache line, the cache access control circuitry is responsive to detecting the hit condition to allow access to any of the data blocks stored in the multiple cache lines forming the merged cache line.

公开(公告)号：US20210279063A1

公开(公告)日：2021-09-09

申请号：US17158276

申请日：2021-01-26

Applicant: Arm Limited

Inventor： Vladimir VASEKIN ,  David Michael BULL ,  Frederic Claude Marie PIRY ,  Alexei FEDOROV

IPC: G06F9/38

Abstract: An apparatus has processing circuitry for executing instructions and fetch circuitry for fetching the instructions for execution. When a branch instruction is encountered by the fetch circuitry, it determines subsequent instructions to be fetched in dependence on an initial branch direction prediction for the branch instruction made by branch prediction circuitry. Value prediction circuitry is used to maintain a predicted result value for one or more instructions, and dispatch circuitry maintains a record of pending instructions that have been fetched by the fetch circuitry and are awaiting execution by the processing circuitry, and selects pending instructions from the record for dispatch to the processing circuitry. When a given instruction whose predicted result value is maintained by the value prediction circuitry has a dependent instruction whose outcome is dependent on a result value of the given instruction, the dispatch circuitry nay be arranged to enable speculative execution of that dependent instruction using the predicted result value of the given instruction. Analysis circuitry is arranged, when the dependent instruction is the branch instruction, to detect a mispredict condition when an additional branch direction prediction for the branch instruction determined using the predicted result value for the given instruction is considered more accurate that the initial branch direction prediction, and the additional branch direction prediction differs to the initial branch direction prediction. On detection of the mispredict condition, a control signal is issued to indicate that the branch instruction has been mispredicted.

公开(公告)号：US20170132010A1

公开(公告)日：2017-05-11

申请号：US14938285

申请日：2015-11-11

Applicant: ARM LIMITED

Inventor： Vladimir VASEKIN ,  Ian Michael CAULFIELD ,  Chiloda Ashan Senarath PATHIRANE

IPC: G06F9/38

CPC classification number: G06F9/3855 ,  G06F9/384

Abstract: An apparatus for data processing and a method of data processing are provided. Data processing operations are performed in response to instructions which reference architectural registers using physical registers to store data values when performing the data processing operations. Mappings between the architectural registers and the physical registers are stored, and when a data hazard condition is identified with respect to out-of-order program execution of an instruction, an architectural register specified in the instruction is remapped to an available physical register. A reorder buffer stores an entry for each destination architectural register specified by the instruction, entries being stored in program order, and an entry specifies a destination architectural register and an original physical register to which the destination architectural register was mapped before the architectural register remapped to an available physical register.