公开(公告)号：US20200073666A1

公开(公告)日：2020-03-05

申请号：US16120674

申请日：2018-09-04

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Muhammad Umar FAROOQ ,  Chris ABERNATHY

IPC: G06F9/38

Abstract: Branch prediction circuitry processes blocks of instructions and provides instruction fetch circuitry with indications of predicted next blocks of instructions to be retrieved from memory. Main branch target storage stores branch target predictions for branch instructions in the blocks of instructions. Secondary branch target storage caches the branch target predictions from the main branch target storage. Look-ups in the secondary branch target storage and the main branch target storage are performed in parallel. The main branch target storage is set-associative and an entry in the main branch target storage comprises multiple ways, wherein each way of the multiple ways stores a branch target prediction for one branch instruction. The branch prediction circuitry stores a way prediction for which of the multiple ways contain the branch target predictions for a predicted next block of instructions and stores a flag associated with the way prediction indicating whether all branch target predictions stored for the predicted next block of instructions in the main branch target storage are also stored in the secondary branch target storage. An active value of the flag suppresses the look-up in the main branch target storage for the predicted next block of instructions.

公开(公告)号：US20230120596A1

公开(公告)日：2023-04-20

申请号：US17505854

申请日：2021-10-20

Applicant: Arm Limited

Inventor： Joseph Michael PUSDESRIS ,  Nicholas Andrew PLANTE ,  Yasuo ISHII ,  Chris ABERNATHY

IPC: G06F9/38 ,  G06F9/30

Abstract: A predicated-loop-terminating branch instruction controls, based on whether a loop termination condition is satisfied, whether the processing circuitry should process a further iteration of a predicated loop body or process a following instruction. If at least one unnecessary iteration of the predicated loop body is processed following a mispredicted-non-termination branch misprediction when the loop termination condition is mispredicted as unsatisfied for a given iteration when it should have been satisfied, processing of the at least one unnecessary iteration of the predicated loop body is predicated to suppress an effect of the at least one unnecessary iteration. When the mispredicted-non-termination branch misprediction is detected for the given iteration of the predicated-loop-terminating branch instruction, in response to determining that a flush suppressing condition is satisfied, flushing of the at least one unnecessary iteration of the predicated loop body is suppressed as a response to the mispredicted-non-termination branch misprediction.

公开(公告)号：US20220318051A1

公开(公告)日：2022-10-06

申请号：US17218425

申请日：2021-03-31

Applicant: Arm Limited

Inventor： Chris ABERNATHY ,  Eric Charles QUINNELL ,  ABHISHEK RAJA ,  Michael David ACHENBACH

IPC: G06F9/48 ,  G06F9/50

Abstract: Circuitry comprises two or more clusters of execution units, each cluster comprising one or more execution units to execute processing instructions; and scheduler circuitry to maintain one or more queues of processing instructions, the scheduler circuitry comprising picker circuitry to select a queued processing instruction for issue to an execution unit of one of the clusters of execution units for execution; in which: the scheduler circuitry is configured to maintain dependency data associated with each queued processing instruction, the dependency data for a queued processing instruction indicating any source operands which are required to be available for use in execution of that queued processing instruction and to inhibit issue of that queued processing instruction until all of the required source operands for that queued processing instruction are available and is configured to be responsive to an indication to the scheduler circuitry of the availability of the given operand as a source operand for use in execution of queued processing instructions; and the scheduler circuitry is responsive to an indication of availability of one or more last awaited source operands for a given queued processing instruction, to inhibit issue by the scheduler circuitry of the given queued processing instruction to an execution unit in a cluster of execution units other than a cluster of execution units containing an execution unit which generated at least one of those last awaited source operands.

公开(公告)号：US20200150967A1

公开(公告)日：2020-05-14

申请号：US16185073

申请日：2018-11-09

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Muhammad Umar FAROOQ ,  Chris ABERNATHY

IPC: G06F9/38 ,  G06F9/30

Abstract: Apparatus and a method of operating the same is disclosed. Instruction fetch circuitry is provided to fetch a block of instructions from memory and branch prediction circuitry to generate branch prediction indications for each branch instruction present in the block of instructions. The branch prediction circuitry is responsive to identification of a first conditional branch instruction in the block of instructions that is predicted to be taken to modify a branch prediction indication generated for the first conditional branch instruction to include a subsequent branch status indicator. When there is a subsequent branch instruction after the first conditional branch instruction in the block of instructions that is predicted to be taken the subsequent branch status indicator has a first value, and otherwise the subsequent branch status indicator has a second value. This supports improved handling of a misprediction as taken.

公开(公告)号：US20200081715A1

公开(公告)日：2020-03-12

申请号：US16124264

申请日：2018-09-07

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Chris ABERNATHY

IPC: G06F9/38 ,  G06F9/30

Abstract: A data processing apparatus is provided that includes a plurality of control flow execution circuits to simultaneously execute a first control flow instruction having a first type and a second control flow instruction having a second type from a plurality of instructions. A control flow prediction update circuit updates at most one of: a prediction of the first control flow instruction based on a result of the first control flow instruction, and a prediction of the second control flow instruction based on a result of the second control flow instruction.

公开(公告)号：US20170185410A1

公开(公告)日：2017-06-29

申请号：US14757576

申请日：2015-12-24

Applicant: ARM LIMITED

Inventor： Chris ABERNATHY ,  Florent BEGON

IPC: G06F9/38 ,  G06F9/30

Abstract: An apparatus has processing circuitry, register rename circuitry and control circuitry which selects one of first and second move handling techniques for handling a move instruction specifying a source logical register and a destination logical register. In the first technique, the register rename circuitry maps the destination logical register of the move to the same physical register as the source logical register. In the second technique, the processing circuitry writes a data value read from a physical register corresponding to the source logical register to a different physical register corresponding to the destination local register. The second technique is selected when the move instruction specifies the same source logical register as one of the source and destination logical registers as an earlier move instruction handled according to the first technique, and the register mapping used for that register when handling the earlier move instruction is still current.

公开(公告)号：US20200073576A1

公开(公告)日：2020-03-05

申请号：US16118610

申请日：2018-08-31

Applicant: Arm Limited

Inventor： Adrian MONTERO ,  Miles Robert DOOLEY ,  Joseph Michael PUSDESRIS ,  Klas Magnus BRUCE ,  Chris ABERNATHY

IPC: G06F3/06 ,  G11B19/04 ,  G06F9/50 ,  G06F12/0862

Abstract: Storage circuitry is provided, that is designed to form part of a memory hierarchy. The storage circuitry comprises receiver circuitry for receiving a request to obtain data from the memory hierarchy. Transfer circuitry causes the data to be stored at a selected destination in response to the request, wherein the selected destination is selected in dependence on at least one selection condition. Tracker circuitry tracks the request while the request is unresolved. If at least one selection condition is met then the destination is the storage circuitry and otherwise the destination is other storage circuitry in the memory hierarchy.

公开(公告)号：US20190377599A1

公开(公告)日：2019-12-12

申请号：US16005811

申请日：2018-06-12

Applicant: Arm Limited

Inventor： . ABHISHEK RAJA ,  Chris ABERNATHY ,  Michael FILIPPO

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/30

Abstract: There is provided a data processing apparatus that includes processing circuitry for executing a plurality of instructions. Storage circuitry stores a plurality of entries, each entry relating to an instruction in the plurality of instructions and including a dependency field. The dependency field stores a data dependency of that instruction on a previous instruction in the plurality of instructions. Scheduling circuitry schedules the execution of the plurality of instructions in an order that depends on each data dependency. When the previous instruction is a single-cycle instruction, the dependency field includes a reference to one of the entries that relates to the previous instruction, otherwise, the data dependency field includes an indication of an output destination of the previous instruction.

公开(公告)号：US20160070576A1

公开(公告)日：2016-03-10

申请号：US14482146

申请日：2014-09-10

Applicant: ARM LIMITED

Inventor： Chris ABERNATHY ,  Florent BEGON ,  Michael Alan FILIPPO

IPC: G06F9/38

CPC classification number: G06F9/3857 ,  G06F9/384

Abstract: A single threaded out-of-order processor 2 includes an architected register file 22 and a speculative register file 20. Speculative register allocation circuitry 24 serves to allocate speculative registers for use in accordance with an allocation sequence and taken from a position determined by a tail point. Read suppression circuitry 30 serves to maintain a boundary pointer corresponding to a position within the allocation sequence such that no speculative register more recently allocated within the allocation sequence than that corresponding to the boundary pointer can have a valid register value. The read suppression circuitry 30 serves to suppress read operations for source operands lying within a read-suppression region delimited by the tail point and the boundary pointer. Separate boundary pointers may be maintained for different types of register values, such as integer register values and floating point register values.

Abstract translation: 单线程无序处理器2包括架构化寄存器文件22和推测寄存器文件20.推测性寄存器分配电路24用于根据分配序列分配推测寄存器，并从由尾部确定的位置 点。 读取抑制电路30用于维持与分配序列内的位置相对应的边界指针，使得在分配序列内最近不再分配比与边界指针对应的推测寄存器可以具有有效的寄存器值。 读取抑制电路30用于抑制位于由尾点和边界指针限定的读取抑制区域内的源操作数的读取操作。 可以为不同类型的寄存器值保持单独的边界指针，例如整数寄存器值和浮点寄存器值。