公开(公告)号：US20240232081A9

公开(公告)日：2024-07-11

申请号：US17973433

申请日：2022-10-25

Applicant: Arm Limited

Inventor： Anton SMEKALOV ,  . ABHISHEK RAJA

IPC: G06F12/0808 ,  G06F12/02

CPC classification number: G06F12/0808 ,  G06F12/0238 ,  G06F2212/1021

Abstract: Each entry in a cache has type information associated therewith to indicate a type associated with the data item stored in that entry. Lookup circuitry responds to a given lookup request by performing a lookup procedure to determine whether a hit is detected, by default performing the lookup procedure for a given subset of multiple supported types. Invalidation circuitry processes an invalidation request specifying invalidation parameters used to determine an invalidation address range and invalidation type information, in order to invalidate any data items held in the cache storage that are both associated with the invalidation address range and have an associated type that is indicated by the invalidation type information. Whilst processing of the invalidation request is yet to be completed, filtering circuitry performs a filtering operation for a received lookup request, in order to determine, in dependence on an address indication provided by the received lookup request and one or more of the invalidation parameters of the invalidation request, intersection indication data identifying, for a given type in the given subset, whether an intersection is considered to exist between any entries that would be accessed during performance of the lookup procedure for the received lookup request for the given type and any entries that will be invalidated during processing of the invalidation request, and operation of the lookup circuitry is controlled in dependence on the intersection indication data.

公开(公告)号：US20240134794A1

公开(公告)日：2024-04-25

申请号：US17973433

申请日：2022-10-24

Applicant: Arm Limited

Inventor： Anton SMEKALOV ,  . ABHISHEK RAJA

IPC: G06F12/0808 ,  G06F12/02

CPC classification number: G06F12/0808 ,  G06F12/0238 ,  G06F2212/1021

Abstract: Each entry in a cache has type information associated therewith to indicate a type associated with the data item stored in that entry. Lookup circuitry responds to a given lookup request by performing a lookup procedure to determine whether a hit is detected, by default performing the lookup procedure for a given subset of multiple supported types. Invalidation circuitry processes an invalidation request specifying invalidation parameters used to determine an invalidation address range and invalidation type information, in order to invalidate any data items held in the cache storage that are both associated with the invalidation address range and have an associated type that is indicated by the invalidation type information. Whilst processing of the invalidation request is yet to be completed, filtering circuitry performs a filtering operation for a received lookup request, in order to determine, in dependence on an address indication provided by the received lookup request and one or more of the invalidation parameters of the invalidation request, intersection indication data identifying, for a given type in the given subset, whether an intersection is considered to exist between any entries that would be accessed during performance of the lookup procedure for the received lookup request for the given type and any entries that will be invalidated during processing of the invalidation request, and operation of the lookup circuitry is controlled in dependence on the intersection indication data.

公开(公告)号：US20210026627A1

公开(公告)日：2021-01-28

申请号：US16521748

申请日：2019-07-25

Applicant: Arm Limited

Inventor： . ABHISHEK RAJA ,  Michael FILIPPO ,  Huzefa Moiz SANJELIWALA ,  Kelvin Domnic GOVEAS

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48

Abstract: Circuitry comprises an instruction decoder to decode a gather load instruction having a vector operand comprising a plurality of vector entries, in which each vector entry defines, at least in part, a respective address from which data is to be loaded; the instruction decoder being configured to generate a set of load operations relating to respective individual addresses in dependence upon the vector operand, each of the set of load operations having a respective identifier which is unique with respect to other load operations in the set, and control circuitry to maintain a data item for the gather load instruction, the data item including a count value representing a number of load operations in the set of load operations awaiting issue for execution; and execution circuitry to execute the set of load operations; the control circuitry being configured, in response to a detection from the count value of the data item associated with a given gather load instruction that the set of load operations generated for the given gather load instruction has reached a predetermined stage relative to execution of all of that set of load operations, to control handling of a consumer instruction, being an instruction which depends upon the completion of the given gather load instruction.

公开(公告)号：US20250110863A1

公开(公告)日：2025-04-03

申请号：US18477625

申请日：2023-09-29

Applicant: Arm Limited

Inventor： . ABHISHEK RAJA

IPC: G06F12/02

Abstract: There is provided an apparatus, system, chip-containing product, method, and storage medium. The apparatus comprises memory access circuitry responsive to one or more types of memory access request, to retrieve specified data items from memory. The apparatus is also provided with local storage circuitry configured to store at least some of the retrieved data items. The local storage circuitry is N-way associative, and N is greater than 1. The apparatus is also provided with control circuitry responsive to an indication that an access request signalled to the local storage circuitry relating to an accessed data item corresponds to a predefined type of memory access request, to implement a restrictive access policy in relation to the accessed data item in the local storage circuitry. The restrictive access policy excludes at least one step of accessing an excluded subset of ways of the local storage circuitry.

公开(公告)号：US20250021480A1

公开(公告)日：2025-01-16

申请号：US18350217

申请日：2023-07-11

Applicant: Arm Limited

Inventor： Natalya BONDARENKO ,  Stefano GHIGGINI ,  Kamil GARIFULLIN ,  Fabian GRUBER ,  . ABHISHEK RAJA ,  Devin S. LAFFORD

IPC: G06F12/0811 ,  G06F12/0862 ,  G06F12/0871

Abstract: Apparatuses, methods, systems, and chip-containing products are disclosed, which relate to an arrangement comprising a level N cache level and a level M cache level, where M is greater than N. The level N cache level comprises a plurality of linefill slots and performs a slot allocation procedure in response to a lookup miss in dependence on a linefill slot occupancy criterion. The slot allocation procedure comprises allocation of an available slot of the plurality of slots to a pending linefill request generated in response to the lookup miss. The level N cache level effects a modification of the slot allocation procedure in dependence on the linefill slot occupancy criterion and is responsive to the linefill slot occupancy criterion being fulfilled to cause a linefill delegation action to be instructed to the level M cache level.

公开(公告)号：US20230067573A1

公开(公告)日：2023-03-02

申请号：US17459130

申请日：2021-08-27

Applicant: Arm Limited

Inventor： . ABHISHEK RAJA

IPC: G06F9/22 ,  G06F9/30

Abstract: A predicated vector load micro-operation specifies a load target address, a destination vector register for which active vector elements of the destination vector register are to be loaded with data associated with addresses identified based on the load target address, and a predicate operand indicative of whether each vector element of the destination vector register is active or inactive. A predetermined type of predicated vector load micro-operation can be issued to the processing circuitry before the predicate operand is determined to meet an availability condition, and if issued in this way memory access circuitry can determine, based on the load target address, whether the predetermined type of predicated vector load micro-operation satisfies a predetermined condition, and if the predetermined condition is unsatisfied, perform a complete vector load assuming all vector elements of the destination vector register are active vector elements, independent of whether the predicate operand when available identifies any inactive vector element of the destination vector register.

公开(公告)号：US20210064377A1

公开(公告)日：2021-03-04

申请号：US16550612

申请日：2019-08-26

Applicant: Arm Limited

Inventor： . ABHISHEK RAJA ,  Rakesh Shaji LAL ,  Michael FILIPPO ,  Glen Andrew HARRIS ,  Vasu KUDARAVALLI ,  Huzefa Moiz SANJELIWALA ,  Jason SETTER

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/34

Abstract: A data processing apparatus is provided that comprises fetch circuitry to fetch an instruction stream comprising a plurality of instructions, including a status updating instruction, from storage circuitry. Status storage circuitry stores a status value. Execution circuitry executes the instructions, wherein at least some of the instructions are executed in an order other than in the instruction stream. For the status updating instruction, the execution circuitry is adapted to update the status value based on execution of the status updating instruction. Flush circuitry flushes, when the status storage circuitry is updated, flushed instructions that appear after the status updating instruction in the instruction stream.

公开(公告)号：US20230185573A1

公开(公告)日：2023-06-15

申请号：US18109297

申请日：2023-02-14

Applicant: Arm Limited

Inventor： . ABHISHEK RAJA

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3806 ,  G06F9/30043

Abstract: An apparatus has processing circuitry, load tracking circuitry and load prediction circuitry. It is determined whether tracking information indicates that there is a risk of target data, corresponding to an address of a speculatively-issued load operation which is speculatively issued (bypassing an older operation) based on a prediction determined by the load prediction circuitry, having changed between the target data being loaded for the speculatively-issued load operation and data being loaded for a given older load operation bypassed by the speculatively-issued load operation. If so, independent of whether the addresses of the speculatively-issued load operation and the given older load operation correspond, at least the speculatively-issued load operation is reissued, even when the prediction is correct. This protects against ordering violations.

公开(公告)号：US20220300329A1

公开(公告)日：2022-09-22

申请号：US17670762

申请日：2022-02-14

Applicant: Arm Limited

Inventor： . ABHISHEK RAJA

IPC: G06F9/50 ,  G06N5/02

Abstract: An apparatus has processing circuitry, load tracking circuitry and load prediction circuitry to determine a prediction for a predicted load operation. It is determined whether the prediction is correct, and whether the tracking information indicates that, for a given younger load operation issued before it is known whether the prediction is correct, there is a risk of second target data associated with that given load operation having changed after having been loaded. Independent of whether the addresses of the predicted load operation and younger load operation correspond, at least the given load operation is re-processed when the prediction is correct and the tracking information indicates there is a risk of the second target data having changes after being loaded. This protects against ordering violations.

公开(公告)号：US20210294607A1

公开(公告)日：2021-09-23

申请号：US16823695

申请日：2020-03-19

Applicant: Arm Limited

Inventor： . ABHISHEK RAJA

IPC: G06F9/30

Abstract: An apparatus comprises processing circuitry to issue load operations to load data from memory. In response to a plural-register-load instruction specifying at least two destination registers to be loaded with data from respective target addresses, the processing circuitry permits issuing of separate load operations corresponding to the plural-register-load instruction. Load tracking circuitry maintains tracking information for one or more issued load operations. When the plural-register-load instruction is subject to an atomicity requirement and the plurality of load operations are issued separately, the load tracking circuitry detects, based on the tracking information, whether a loss-of-atomicity condition has occurred for the load operations corresponding to the plural-register-load instruction, and requests re-processing of the plural-register-load instruction when the loss-of-atomicity condition is detected.