公开(公告)号：US20200073666A1

公开(公告)日：2020-03-05

申请号：US16120674

申请日：2018-09-04

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Muhammad Umar FAROOQ ,  Chris ABERNATHY

IPC: G06F9/38

Abstract: Branch prediction circuitry processes blocks of instructions and provides instruction fetch circuitry with indications of predicted next blocks of instructions to be retrieved from memory. Main branch target storage stores branch target predictions for branch instructions in the blocks of instructions. Secondary branch target storage caches the branch target predictions from the main branch target storage. Look-ups in the secondary branch target storage and the main branch target storage are performed in parallel. The main branch target storage is set-associative and an entry in the main branch target storage comprises multiple ways, wherein each way of the multiple ways stores a branch target prediction for one branch instruction. The branch prediction circuitry stores a way prediction for which of the multiple ways contain the branch target predictions for a predicted next block of instructions and stores a flag associated with the way prediction indicating whether all branch target predictions stored for the predicted next block of instructions in the main branch target storage are also stored in the secondary branch target storage. An active value of the flag suppresses the look-up in the main branch target storage for the predicted next block of instructions.

公开(公告)号：US20220107807A1

公开(公告)日：2022-04-07

申请号：US17064983

申请日：2020-10-07

Applicant: Arm Limited

Inventor： Michael Brian SCHINZLER ,  Yasuo ISHII ,  Muhammad Umar FAROOQ ,  Jason Lee SETTER

IPC: G06F9/30 ,  G06F12/0875 ,  G06F9/38

Abstract: An apparatus and method are provided for processing instructions fetched from memory. Decode circuitry is used to decode the fetched instructions in order to produce decoded instructions, and downstream circuitry then processes the decoded instructions in order to perform the operations specified by those decoded instructions. Dispatch circuitry is arranged to dispatch to the downstream circuitry up to N decoded instructions per dispatch cycle, and is arranged to determine, based on a given candidate sequence of decoded instructions being considered for dispatch in a given dispatch cycle, whether at least one resource conflict within the downstream circuitry would occur in the event that the given candidate sequence of decoded instructions is dispatched in the given dispatch cycle. The dispatch circuitry has resource checking circuitry arranged, by default, to perform a resource checking operation during the given dispatch cycle to generate, for the given candidate sequence of decoded instructions, resource conflict information used to determine whether a resource conflict would occur. Resource conflict information cache storage is provided to maintain, for one or more sequences of decoded instructions, associated resource conflict information. In the event that the given candidate sequence matches one of the sequences for which associated resource conflict information is cached, the dispatch circuitry employs the associated cached resource conflict information to determine whether a resource conflict would occur, instead of invoking the resource checking circuitry to perform the resource checking operation.

公开(公告)号：US20200150967A1

公开(公告)日：2020-05-14

申请号：US16185073

申请日：2018-11-09

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Muhammad Umar FAROOQ ,  Chris ABERNATHY

IPC: G06F9/38 ,  G06F9/30

Abstract: Apparatus and a method of operating the same is disclosed. Instruction fetch circuitry is provided to fetch a block of instructions from memory and branch prediction circuitry to generate branch prediction indications for each branch instruction present in the block of instructions. The branch prediction circuitry is responsive to identification of a first conditional branch instruction in the block of instructions that is predicted to be taken to modify a branch prediction indication generated for the first conditional branch instruction to include a subsequent branch status indicator. When there is a subsequent branch instruction after the first conditional branch instruction in the block of instructions that is predicted to be taken the subsequent branch status indicator has a first value, and otherwise the subsequent branch status indicator has a second value. This supports improved handling of a misprediction as taken.

公开(公告)号：US20220342671A1

公开(公告)日：2022-10-27

申请号：US17241365

申请日：2021-04-27

Applicant: Arm Limited

Inventor： Michael Brian SCHINZLER ,  Muhammad Umar FAROOQ ,  Yasuo ISHII

IPC: G06F9/38 ,  G06F9/32 ,  G06F9/30

Abstract: Aspects of the present disclosure relate an apparatus comprising fetch circuitry and instruction storage circuitry. The fetch circuitry is to fetch instructions for execution by execution circuitry. The instruction storage circuitry is to store temporary copies of fetched instructions. The fetch circuitry is configured to preferentially fetch instructions from the instruction storage circuitry. The instruction storage circuitry is configured to, responsive to a storage condition being met, begin storing copies of consecutive fetched instructions, the storage condition indicating a utility of a current fetched instruction; and to, responsive to determining that a number of said stored consecutive instructions has reached a storage threshold, cease storing copies of subsequent fetched instructions.

公开(公告)号：US20210271486A1

公开(公告)日：2021-09-02

申请号：US16806063

申请日：2020-03-02

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Joseph Michael PUSDESRIS ,  Muhammad Umar FAROOQ

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/50

Abstract: An apparatus has processing circuitry, and history storage circuitry to store local history records. Each local history record corresponds to a respective subset of instruction addresses and tracks a sequence of observed instruction behaviour observed for successive instances of instructions having addresses in that subset. Pointer storage circuitry to store a shared pointer shared between the local history records. The shared pointer indicates a common storage position reached in each local history record. Prediction circuitry determines predicted instruction behaviour for a given instruction address based on a selected portion of a selected local history record stored in the history storage circuitry. The prediction circuitry selects the selected local history record based on the given instruction address and selects the selected portion based on the shared pointer.

公开(公告)号：US20180293166A1

公开(公告)日：2018-10-11

申请号：US15479348

申请日：2017-04-05

Applicant: ARM Limited

Inventor： Michael FILIPPO ,  Klas Magnus BRUCE ,  Vasu KUDARAVALLI ,  Adam GEORGE ,  Muhammad Umar FAROOQ ,  Joseph Michael PUSDESRIS

IPC: G06F12/0811 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/0815 ,  G06F11/10

CPC classification number: G06F12/0811 ,  G06F11/1064 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/0891 ,  G06F2212/452 ,  G06F2212/62

Abstract: A cache hierarchy and a method of operating the cache hierarchy are disclosed. The cache hierarchy comprises a first cache level comprising an instruction cache, and predecoding circuitry to perform a predecoding operation on instructions having a first encoding format retrieved from memory to generate predecoded instructions having a second encoding format for storage in the instruction cache. The cache hierarchy further comprises a second cache level comprising a cache and the first cache level instruction cache comprises cache control circuitry to control an eviction procedure for the instruction cache in which a predecoded instruction having the second encoding format which is evicted from the instruction cache is stored at the second cache level in the second encoding format. This enables the latency and power cost of the predecoding operation to be avoided when the predecoded instruction is then retrieved from the second cache level for storage in the first level instruction cache again.

公开(公告)号：US20240028241A1

公开(公告)日：2024-01-25

申请号：US17871332

申请日：2022-07-22

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Steven Daniel MACLEAN ,  Nicholas Andrew PLANTE ,  Muhammad Umar FAROOQ ,  Michael Brian SCHINZLER ,  Nicholas Todd HUMPHRIES ,  Glen Andrew HARRIS

IPC: G06F3/06

CPC classification number: G06F3/065 ,  G06F3/0604 ,  G06F3/0673

Abstract: There is provided a data processing apparatus in which decode circuitry receives a memory copy instruction containing an indication of a source area of memory, an indication of a destination area of memory, and an indication of a remaining copy length. In response to receiving the memory copy instruction, the decode circuitry generates at least one active memory copy operation or a null memory copy operation. The active memory copy operation causes one or more execution units to perform a memory copy from part of the source area of memory to part of the destination area of memory and the null memory copy operation leaves the destination area of memory unmodified.

公开(公告)号：US20230195466A1

公开(公告)日：2023-06-22

申请号：US17554573

申请日：2021-12-17

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Muhammad Umar FAROOQ ,  William Elton BURKY ,  Michael Brian SCHINZLER ,  Jason Lee SETTER ,  David Gum LIM

IPC: G06F9/38

CPC classification number: G06F9/384 ,  G06F9/3867

Abstract: A data processing apparatus is provided that comprises rename circuitry for performing a register rename stage of a pipeline in respect of a stream of operations. Move elimination circuitry performs a move elimination operation on the stream of operations in which a move operation is eliminated and the register rename stage performs an adjustment of an identity of registers in the stream of operations to compensate for the move operation being eliminated and demotion circuitry reverses or inhibits the adjustment in response to one or more conditions being met.

公开(公告)号：US20180121203A1

公开(公告)日：2018-05-03

申请号：US15335741

申请日：2016-10-27

Applicant: ARM LIMITED

Inventor： Yasuo ISHII ,  Michael FILIPPO ,  Muhammad Umar FAROOQ

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3806

Abstract: An apparatus comprises a branch target buffer (BTB) to store predicted target addresses of branch instructions. In response to a fetch block address identifying a fetch block comprising two or more program instructions, the BTB performs a lookup to identify whether it stores one or more predicted target addresses for one or more branch instructions in the fetch block. When the BTB is identified in the lookup as storing predicted target addresses for more than one branch instruction in said fetch block, branch target selecting circuitry selects a next fetch block address from among the multiple predicted target addresses returned in the lookup. A shortcut path bypassing the branch target selecting circuitry is provided to forward a predicted target address identified in the lookup as the next fetch block address when a predetermined condition is satisfied.

公开(公告)号：US20220107898A1

公开(公告)日：2022-04-07

申请号：US17060624

申请日：2020-10-01

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  James David DUNDAS ,  Chang Joo LEE ,  Muhammad Umar FAROOQ

IPC: G06F12/0864 ,  G06F12/0811 ,  G06F12/0873 ,  G06F12/121

Abstract: An apparatus comprises first-level and second-level set-associative caches each comprising the same number of sets of cache entries. Indexing circuitry generates, based on a lookup address, a set index identifying which set of the first-level set-associative cache or the second-level set-associative cache is a selected set of cache entries to be looked up for information associated with the lookup address. The indexing circuitry generates the set index using an indexing scheme which maps the lookup address to the same set index for both the first-level set-associative cache and the second-level set-associative cache. This can make migration of cached information between the cache levels more efficient, which can be particularly useful for caches with high access frequency, such as branch target buffers for a branch predictor.