公开(公告)号：US11954040B2

公开(公告)日：2024-04-09

申请号：US16901720

申请日：2020-06-15

Applicant: Arm Limited

Inventor： Alejandro Rico Carro ,  Douglas Joseph ,  Saurabh Pijuskumar Sinha

IPC: G06F12/08 ,  G06F12/06 ,  G06F12/0811 ,  G06F12/0895 ,  G06F12/0897

CPC classification number: G06F12/0897 ,  G06F12/0646 ,  G06F12/0811 ,  G06F12/0895 ,  G06F2212/1012 ,  G06F2212/283

Abstract: Various implementations described herein are directed to device. The device may include a first tier having a processor and a first cache memory that are coupled together via control logic to operate as a computing architecture. The device may include a second tier having a second cache memory that is coupled to the first cache memory. Also, the first tier and the second tier may be integrated together with the computing architecture to operate as a stackable cache memory architecture.

公开(公告)号：US20210390059A1

公开(公告)日：2021-12-16

申请号：US16901720

申请日：2020-06-15

Applicant: Arm Limited

Inventor： Alejandro Rico Carro ,  Douglas Joseph ,  Saurabh Pijuskumar Sinha

IPC: G06F12/0897 ,  G06F12/0895 ,  G06F12/0811 ,  G06F12/06

Abstract: Various implementations described herein are directed to device. The device may include a first tier having a processor and a first cache memory that are coupled together via control logic to operate as a computing architecture. The device may include a second tier having a second cache memory that is coupled to the first cache memory. Also, the first tier and the second tier may be integrated together with the computing architecture to operate as a stackable cache memory architecture.