公开(公告)号：US20230195466A1

公开(公告)日：2023-06-22

申请号：US17554573

申请日：2021-12-17

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Muhammad Umar FAROOQ ,  William Elton BURKY ,  Michael Brian SCHINZLER ,  Jason Lee SETTER ,  David Gum LIM

IPC: G06F9/38

CPC classification number: G06F9/384 ,  G06F9/3867

Abstract: A data processing apparatus is provided that comprises rename circuitry for performing a register rename stage of a pipeline in respect of a stream of operations. Move elimination circuitry performs a move elimination operation on the stream of operations in which a move operation is eliminated and the register rename stage performs an adjustment of an identity of registers in the stream of operations to compensate for the move operation being eliminated and demotion circuitry reverses or inhibits the adjustment in response to one or more conditions being met.

公开(公告)号：US20220107807A1

公开(公告)日：2022-04-07

申请号：US17064983

申请日：2020-10-07

Applicant: Arm Limited

Inventor： Michael Brian SCHINZLER ,  Yasuo ISHII ,  Muhammad Umar FAROOQ ,  Jason Lee SETTER

IPC: G06F9/30 ,  G06F12/0875 ,  G06F9/38

Abstract: An apparatus and method are provided for processing instructions fetched from memory. Decode circuitry is used to decode the fetched instructions in order to produce decoded instructions, and downstream circuitry then processes the decoded instructions in order to perform the operations specified by those decoded instructions. Dispatch circuitry is arranged to dispatch to the downstream circuitry up to N decoded instructions per dispatch cycle, and is arranged to determine, based on a given candidate sequence of decoded instructions being considered for dispatch in a given dispatch cycle, whether at least one resource conflict within the downstream circuitry would occur in the event that the given candidate sequence of decoded instructions is dispatched in the given dispatch cycle. The dispatch circuitry has resource checking circuitry arranged, by default, to perform a resource checking operation during the given dispatch cycle to generate, for the given candidate sequence of decoded instructions, resource conflict information used to determine whether a resource conflict would occur. Resource conflict information cache storage is provided to maintain, for one or more sequences of decoded instructions, associated resource conflict information. In the event that the given candidate sequence matches one of the sequences for which associated resource conflict information is cached, the dispatch circuitry employs the associated cached resource conflict information to determine whether a resource conflict would occur, instead of invoking the resource checking circuitry to perform the resource checking operation.

公开(公告)号：US20240329999A1

公开(公告)日：2024-10-03

申请号：US18129979

申请日：2023-04-03

Applicant: Arm Limited

Inventor： Chang Joo LEE ,  Jason Lee SETTER ,  Julia Kay LANIER ,  Michael Brian SCHINZLER ,  Yasuo ISHII

IPC: G06F9/38

CPC classification number: G06F9/3806 ,  G06F9/3861 ,  G06F9/3802

Abstract: An apparatus is provided for limiting the effective utilisation of an instruction fetch queue. The instruction fetch entries are used to control the prefetching of instructions from memory, such that those instructions are stored in an instruction cache prior to being required by execution circuitry while executing a program. By limiting the effective utilisation of the instruction fetch queue, fewer instructions will be prefetched and fewer instructions will be allocated to the instruction cache, thus causing fewer evictions from the instruction cache. In the event that the instruction fetch entries are for instructions that are unnecessary to the program, the pollution of the instruction cache with these unnecessary instructions can be mitigated.