公开(公告)号：US20150039968A1

公开(公告)日：2015-02-05

申请号：US14283517

申请日：2014-05-21

Applicant: ARM LIMITED

Inventor： Luc ORION

IPC: G06F11/10

CPC classification number: G06F11/1076 ,  G06F11/1064 ,  G06F2211/1088

Abstract: A memory 10 stores a data block comprising a plurality of data values DV. An error code, such as an error correction code ECC, is associated with the memory and has a value dependent upon the plurality of data values which form the data block stored within the memory. If a partial write is performed on a data block, then the ECC information becomes invalid and is marked with an ECC_invalid flag. The intent is avoiding the need to read all data values to compute the ECC and thus save time and energy. The memory may be a cache line 28 within a level 1 cache memory 10. Memory scrub control circuitry 38 performs periodic memory scrub operations which trigger flushing of partially written cache lines back to main memory.

Abstract translation: 存储器10存储包括多个数据值DV的数据块。 诸如纠错码ECC的错误代码与存储器相关联，并且具有取决于形成存储在存储器内的数据块的多个数据值的值。 如果在数据块上执行部分写入，则ECC信息变为无效，并用ECC_invalid标志标记。 目的是避免读取所有数据值来计算ECC，从而节省时间和精力。 存储器可以是级1高速缓冲存储器10内的高速缓存线28.存储器擦除控制电路38执行周期性的存储器擦除操作，其触发将部分写入的高速缓存行刷新回主存储器。

公开(公告)号：US20200082280A1

公开(公告)日：2020-03-12

申请号：US16541531

申请日：2019-08-15

Applicant: Arm Limited

Inventor： Luc ORION ,  Houdhaifa BOUZGUARROU ,  Guillaume BOLBENES ,  Eddy LAPEYRE

IPC: G06N5/04 ,  G06N5/00 ,  G06N20/00 ,  G06F12/0862

Abstract: An apparatus comprises: a prediction storage structure comprising a plurality of prediction state entries representing instances of predicted instruction behaviour; prediction training circuitry to perform a training operation to train the prediction state entries based on actual instruction behaviour; prediction circuitry to output at least one control signal for triggering a speculative operation based on the predicted instruction behaviour represented by a prediction state entry for which the training operation has provided sufficient confidence in the predicted instruction behaviour; an allocation filter comprising at least one allocation filter entry representing a failed predicted instruction behaviour for which the training operation failed to provide said sufficient confidence; and prediction allocation circuitry to prevent allocation of a new entry in the prediction storage structure for a failed predicted instruction behaviour represented by an allocation filter entry of the allocation filter.

公开(公告)号：US20190258485A1

公开(公告)日：2019-08-22

申请号：US15900914

申请日：2018-02-21

Applicant: Arm Limited

Inventor： Houdhaifa BOUZGARROU ,  Guillaume BOLBENES ,  Eddy LAPEYRE ,  Luc ORION

IPC: G06F9/30

Abstract: An apparatus is provided to perform branch prediction in respect of a plurality of instructions divided into a plurality of blocks. Receiving circuitry receives references to at least two blocks in the plurality of blocks. Branch prediction circuitry performs at least two branch predictions at a time. The branch predictions are performed in respect of the at least two blocks and the at least two blocks are non-contiguous.

公开(公告)号：US20190138315A1

公开(公告)日：2019-05-09

申请号：US15806605

申请日：2017-11-08

Applicant: Arm Limited

Inventor： Guillaume BOLBENES ,  Houdhaifa BOUZGUARROU ,  Luc ORION ,  Eddy LAPEYRE

IPC: G06F9/38 ,  G06F9/30

Abstract: Program flow prediction circuitry comprises a history register to store history data for at least one or more most recently executed branch instructions; a memory to store a plurality of sets of weight values, one set for each of a group of portions of one or more bits of the history data; access circuitry to access, for a current branch instruction to be predicted, a weight value for each of the portions of one or more bits of the history data by selecting from the set of weight values in dependence upon a current value of the portions of the history data; a combiner to generate a combined weight value by combining the weight values accessed by the access circuitry; a comparator to compare the combined weight value with a prediction threshold value to detect whether or not a branch represented by the current branch instruction is predicted to be taken; and weight modifier circuitry to modify the accessed weight values in dependence upon a resolution of whether the branch represented by the current branch instruction is taken or not.

公开(公告)号：US20200081717A1

公开(公告)日：2020-03-12

申请号：US16541507

申请日：2019-08-15

Applicant: Arm Limited

Inventor： Luc ORION ,  Houdhaifa BOUZGUARROU ,  Guillaume BOLBENES ,  Eddy LAPEYRE

IPC: G06F9/38

Abstract: Branch prediction circuitry comprises: a return address prediction structure to store at least one predicted return address; and a branch target buffer (BTB) structure comprising entries each for specifying predicted branch information for a corresponding block of instructions. Within at least a subset of entries of the BTB structure, each entry specifies the predicted branch information with an encoding incapable of simultaneously indicating both: that the corresponding block of instructions is predicted to include a return branch instruction (for which the return address prediction structure is used to predict the target address); and the predicted target address for the return branch instruction. This can provide a more efficient BTB structure which requires less circuit area and power for a given level of branch prediction performance.

公开(公告)号：US20200065105A1

公开(公告)日：2020-02-27

申请号：US16108115

申请日：2018-08-22

Applicant: Arm Limited

Inventor： Houdhaifa BOUZGUARROU ,  Guillaume BOLBENES ,  Eddy LAPEYRE ,  Luc ORION

IPC: G06F9/38

Abstract: An apparatus and method are provided for detecting regularity in a number of occurrences of an event observed during multiple instances of a counting period. The apparatus has regularity detection circuitry for seeking to detect such a regularity, and a storage providing a storage entry having a count value field to store a count value and a confidence indication field to indicate a confidence in the regularity. The regularity detection circuitry is arranged to consider the multiple instances of the counting period in pairs, for one instance in the pair the regularity detection circuitry incrementing the count value following each occurrence of the event, and for the other instance in the pair the regularity detection circuitry decrementing the count value following each occurrence of the event. Check circuitry is then arranged, following completion of both counting periods in the pair, to adjust the confidence indication to indicate an increased confidence when it is determined that the count value has returned to an initial value, and otherwise to adjust the confidence indication to indicate a decreased confidence and to reset the count value to the initial value. Such an approach provides a particularly storage efficient mechanism for seeking to detect regularity in a number of occurrences of an event.

公开(公告)号：US20200050458A1

公开(公告)日：2020-02-13

申请号：US16100344

申请日：2018-08-10

Applicant: Arm Limited

Inventor： Houdhaifa BOUZGUARROU ,  Luc ORION ,  Guillaume BOLBENES ,  Eddy LAPEYRE

IPC: G06F9/38 ,  G06F9/32 ,  G06F9/30

Abstract: An apparatus and method are provided for performing branch prediction. The apparatus has processing circuitry to execute instructions, and branch prediction circuitry for making branch outcome predictions in respect of branch instructions. The branch prediction circuitry includes loop minimum iteration prediction circuitry having one or more entries, where each entry is associated with a loop controlling branch instruction that controls repeated execution of a loop comprising a number of instructions. During a training phase for an entry, the loop minimum iteration prediction circuitry seeks to identify a minimum number of iterations of the loop. The loop minimum iteration prediction circuitry is then arranged, when the training phase has successfully identified a minimum number of iterations, to subsequently identify a branch outcome prediction for the associated loop controlling branch instruction for use during the minimum number of iterations. It has been found that such an approach can significantly improve prediction accuracy for loop controlling branch instructions associated with loops that do not have a stable total number of iterations.