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公开(公告)号：US20210124586A1
公开(公告)日：2021-04-29
申请号：US16662438
申请日：2019-10-24
申请人： Arm Limited
IPC分类号： G06F9/38 , G06F12/0875 , G06F9/30
摘要： An apparatus and method are provided for handling incorrect branch direction predictions. The apparatus has processing circuitry for executing instructions, branch prediction circuitry for making branch direction predictions in respect of branch instructions, and fetch circuitry for fetching instructions from an instruction cache in dependence on the branch direction predictions and for forwarding the fetched instructions to the processing circuitry for execution. A cache location buffer stores cache location information for a given branch instruction for which accuracy of the branch direction predictions made by the branch prediction circuitry is below a determined threshold. The cache location information identifies where within the instruction cache one or more instructions are stored that will need to be executed in the event that a subsequent branch direction prediction made for the given branch instruction is incorrect. Control circuitry is responsive to such a subsequent branch direction prediction to obtain from the cache location buffer the cache location information and to provide the obtained cache location information to the fetch circuitry to enable the fetch circuitry to retrieve from the instruction cache the one or more instructions that are to be executed in the event that the processing circuitry does determine that the subsequent branch direction prediction was incorrect.
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公开(公告)号：US20210397455A1
公开(公告)日：2021-12-23
申请号：US16906259
申请日：2020-06-19
申请人： Arm Limited
摘要： A data processing apparatus is provided, which is able to provide predictions for hard to predict instructions. Prediction circuitry generates predictions relating to predictable instructions in a stream, where the prediction circuitry comprises storage circuitry to store, in respect of each of the predictable instructions, a reference to a set of monitored instructions in the stream to be used for generating predictions for the predictable instructions. Processing circuitry receives the predictions from the prediction circuitry and executes the predictable instructions in the stream using the predictions. Programmable instruction correlation parameter storage circuitry stores a given correlation parameter between a given predictable instruction in the stream and a subset of the set of monitored instructions of the given predictable instruction, to assist the prediction circuitry in generating the predictions. If the programmable instruction correlation parameter storage circuitry is currently storing the given correlation parameter, the prediction circuitry generates a given prediction relating to the given predictable instruction based on the subset of the set of monitored instructions indicated in the programmable instruction correlation parameter storage circuitry. Otherwise the prediction circuitry generates the given prediction relating to the given predictable instruction based on the set of monitored instructions indicated in the storage circuitry.
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公开(公告)号：US20200065111A1
公开(公告)日：2020-02-27
申请号：US16106382
申请日：2018-08-21
申请人： Arm Limited
发明人： Houdhaifa BOUZGUARROU , Guillaume BOLBENES , Frederic Claude Marie PIRY , Albin Pierrick TONNERRE
摘要： An apparatus and method are provided for performing branch prediction. The apparatus has processing circuitry for executing instructions, and branch prediction circuitry for making branch outcome predictions in respect of branch instructions. The branch prediction circuitry includes loop prediction circuitry having a plurality of entries, where each entry is used to maintain branch outcome prediction information for a loop controlling branch instruction that controls repeated execution of a loop comprising a number of instructions. The branch prediction circuitry is arranged to analyse blocks of instructions and to produce a prediction result for each block that is dependent on branch outcome predictions made for any branch instructions appearing in the associated block. A prediction queue then stores the prediction results produced by the branch prediction circuitry in order to determine the instructions to be executed by the processing circuitry. When the block of instructions being analysed comprises a loop controlling branch instruction that has an active entry in the loop prediction circuitry, and a determined condition is detected in respect of the associated loop, the loop prediction circuitry is arranged to produce a prediction result that identifies multiple iterations of the loop. This can significantly boost prediction bandwidth for certain types of loop.
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公开(公告)号：US20170337133A1
公开(公告)日：2017-11-23
申请号：US15156484
申请日：2016-05-17
申请人： ARM Limited
IPC分类号： G06F12/0891 , G06F12/1027 , G06F12/1009 , G06F12/121
CPC分类号： G06F12/126 , G06F2212/68
摘要： A data processing system 2 incorporates a cache system 4 having a cache memory 6 and a cache controller 10, 12, 14, 16, 18. The cache controller selects for cache entry eviction using a primary eviction policy. This primary eviction policy may identify a plurality of candidates for eviction with an equal preference for eviction. The cache controller provides a further selection among this plurality of candidates based upon content data read from those candidates themselves as part of the cache access operation which resulted in the cache miss leading to the cache replacement requiring the victim selection. The content data used to steer this second stage of victim selection may include transience specifying data and, for example, in the case of a cache memory comprising a translation lookaside buffer 6, page size data, type of translation data, memory type data, permission data and the like.
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公开(公告)号：US20240232228A1
公开(公告)日：2024-07-11
申请号：US18152946
申请日：2023-01-11
申请人： Arm Limited
IPC分类号： G06F16/28 , G06F16/22 , G06F16/2457
CPC分类号： G06F16/285 , G06F16/2228 , G06F16/24578
摘要： An apparatus has a data storage structure to store data items tagged by respective tag values and stores, in association with each data item, a respective tag group identifier to identify other data items having a same tag value within a collection of data items. The apparatus also has tag match circuitry to identify one or more hitting data items. Prioritisation circuitry is provided to select candidate data items which, relative to any other data items in the particular collection of data items having the same tag group identifier as the selected candidate data item is favoured according to an ordering of the data items. The prioritisation circuitry selects the one or more candidate data items before the identification of the hitting data items is available from the tag match circuitry. Data item selection circuitry selects a candidate data item for which the tag match circuitry detected a match.
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公开(公告)号：US20230214222A1
公开(公告)日：2023-07-06
申请号：US17566157
申请日：2021-12-30
申请人： Arm Limited
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/3867
摘要： Aspects of the present disclosure relate to an apparatus. Instruction information generation circuitry generates instruction information. Instruction information storage circuitry comprises a plurality of elements having physical sub-elements configured to temporarily store units of instruction information, Allocation circuitry is configured to receive, from the instruction information generation circuitry, given instruction information, It determines a mapping of a plurality of ordered virtual sub-elements, such that each virtual sub-element maps onto a respective one of said physical sub-elements. The given instruction information is stored into the virtual sub-elements of a given element, according to the mapping, such that at least one virtual sub-element lower in said order has a higher priority than at least one virtual sub-element higher in said order. Sub-element deactivation circuitry is configured to track usage of said virtual sub-elements across the plurality of elements and adaptively deactivate virtual sub-elements.
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公开(公告)号：US20230133144A1
公开(公告)日：2023-05-04
申请号：US17518661
申请日：2021-11-04
申请人： Arm Limited
摘要： There is provided a data processing apparatus and method. The data processing apparatus comprises a filter circuit comprising storage circuitry to store program counter values and to assert a trigger signal in response to a lookup operation using a current program counter value hitting in the storage circuitry. The processing apparatus comprises a processing unit to generate an output in response to the trigger signal. The processing apparatus is provided with resolution circuitry, associated with a downstream processing stage, to determine whether the output is of use, and in that event to assert a false miss indication in the absence of the processing unit having been triggered to produce the output. The filter circuit is configured to maintain a trigger sensitivity metric in dependence on the false miss indication, and the chosen number of bits employed when performing the lookup operation is dependent on the trigger sensitivity metric.
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公开(公告)号：US20210232400A1
公开(公告)日：2021-07-29
申请号：US16775431
申请日：2020-01-29
申请人： Arm Limited
摘要： A branch predictor provides a predicted branch instruction outcome for a current block of at least one instruction. The branch predictor comprises branch prediction tables to store branch prediction entries providing branch prediction information; lookup circuitry to perform, based on indexing information associated with the current block, a table lookup in a looked up subset of the branch prediction tables; and prediction generating circuitry to generate the predicted branch instruction outcome for the current block based on the branch prediction information in the branch prediction entries looked up in the looked up subset of branch prediction tables. The looked up subset of branch prediction tables is selected based on lookup filtering information obtained for the current block. Lookups to tables other than the looked up subset are suppressed.
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公开(公告)号：US20210064528A1
公开(公告)日：2021-03-04
申请号：US16550607
申请日：2019-08-26
申请人： Arm Limited
发明人： Yasuo ISHII , Matthew Andrew RAFACZ , Guillaume BOLBENES , Houdhaifa BOUZGUARROU , . ABHISHEK RAJA
IPC分类号： G06F12/0808 , G06F12/1027
摘要： A data processing apparatus is provided. Cache circuitry caches data, the data being indexed according to execution contexts of processing circuitry. Receive circuitry receives invalidation requests each referencing a specific execution context in the execution contexts. Invalidation circuitry invalidates at least some of the data in the cache circuitry and filter circuitry filters the invalidation requests based on at least one condition and, when the condition is met, causes the invalidation circuitry to invalidate the data in the cache circuitry.
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公开(公告)号：US20200082280A1
公开(公告)日：2020-03-12
申请号：US16541531
申请日：2019-08-15
申请人： Arm Limited
IPC分类号： G06N5/04 , G06N5/00 , G06N20/00 , G06F12/0862
摘要： An apparatus comprises: a prediction storage structure comprising a plurality of prediction state entries representing instances of predicted instruction behaviour; prediction training circuitry to perform a training operation to train the prediction state entries based on actual instruction behaviour; prediction circuitry to output at least one control signal for triggering a speculative operation based on the predicted instruction behaviour represented by a prediction state entry for which the training operation has provided sufficient confidence in the predicted instruction behaviour; an allocation filter comprising at least one allocation filter entry representing a failed predicted instruction behaviour for which the training operation failed to provide said sufficient confidence; and prediction allocation circuitry to prevent allocation of a new entry in the prediction storage structure for a failed predicted instruction behaviour represented by an allocation filter entry of the allocation filter.
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