公开(公告)号：US20230289186A1

公开(公告)日：2023-09-14

申请号：US18006806

申请日：2021-07-05

Applicant: ARM LIMITED

Inventor： Nigel John STEPHENS ,  Jelena MILANOVIC ,  David Hennah MANSELL

IPC: G06F9/30

CPC classification number: G06F9/3016 ,  G06F9/30105

Abstract: A data transfer instruction is provided which specifies register addressing information for identifying a target portion of the register storage. In response to the data transfer instruction, instruction decoding circuitry controls processing circuitry to perform a data transfer operation to transfer data to or from the target portion of the register storage. The register addressing information includes at least: a base register identifier identifying a base register of the register storage for storing a base value; and an immediate value specified in an encoding of the data transfer instruction, the immediate value representing a value to be added to the base value to provide an index value for selecting the target portion of the register storage. This can be useful to provide an instruction set architecture which supports code that is scalable to variable data structure sizes, and which supports loop unrolling.

公开(公告)号：US20210042261A1

公开(公告)日：2021-02-11

申请号：US16531210

申请日：2019-08-05

Applicant: Arm Limited

Inventor： Jelena MILANOVIC ,  Lee Evan EISEN ,  Nigel John STEPHENS

IPC: G06F15/80 ,  G06F9/30

Abstract: Data processing apparatus comprises processing circuitry to apply processing operations to one or more data items of a linear array comprising a plurality, n, of data items at respective positions in the linear array, the processing circuitry being configured to access an array of n×n storage locations, where n is an integer greater than one, the processing circuitry comprising: instruction decoder circuitry to decode program instructions; and instruction processing circuitry to execute instructions decoded by the instruction decoder circuitry; wherein the instruction decoder circuitry is responsive to an array access instruction, to control the instruction processing circuitry to access, as a linear array, a set of n storage locations arranged in an array direction selected, under control of the array access instruction, from a set of candidate array directions comprising at least a first array direction and a second array direction different to the first array direction.

公开(公告)号：US20210026629A1

公开(公告)日：2021-01-28

申请号：US16630622

申请日：2018-07-02

Applicant: ARM LIMITED

Inventor： Mbou EYOLE ,  Nigel John STEPHENS

IPC: G06F9/30 ,  G06F9/38

Abstract: Vector interleaving techniques in a data processing apparatus are disclosed, comprising apparatuses, instructions, methods of operating the apparatuses, and simulator implementations. A vector interleaving instruction specifies a first source register, second source register, and destination register. A first set of input data items is retrieved from the first source register and a second set of input data items from the second source register. A data processing operation is performed on selected input data item pairs taken from the first and second set of input data items to generate a set of result data items, which are stored as a result data vector in the destination register. First source register dependent result data items are stored in a first set of alternating positions in the destination data vector and second source register dependent result data items are stored in a second set of alternating positions in the destination data vector.

公开(公告)号：US20200249942A1

公开(公告)日：2020-08-06

申请号：US16424718

申请日：2019-05-29

Applicant: Arm Limited

Inventor： David Raymond LUTZ ,  Neil BURGESS ,  Christopher Neal HINDS ,  Nigel John STEPHENS

IPC: G06F9/30 ,  H03M7/24

Abstract: An apparatus is provided, that includes an instruction decoder responsive to an anchored-data processing instruction, to generate one or more control signals. Conversion circuitry is responsive to the one or more control signals to perform a conversion from a data value to an anchored-data select value. The conversion is based on anchor metadata indicative of a given range of significance for the anchored-data select value. Output circuitry is responsive to the one or more control signals, to write the anchored-data select value to a register.

公开(公告)号：US20180293078A1

公开(公告)日：2018-10-11

申请号：US15769558

申请日：2016-09-14

Applicant: ARM LIMITED

Inventor： Giacomo GABRIELLI ,  Nigel John STEPHENS

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3865 ,  G06F9/3001 ,  G06F9/30036

Abstract: Processing circuitry supports a first type of vector arithmetic instruction specifying at least a first input vector. When at least one exceptional condition is detected for an arithmetic operation performed for a first active data element of the first input vector in a predetermined sequence, the processing circuitry performs at least one response action. When the at least one exceptional condition is detected for a given active data element other than the first active data element in the predetermined sequence, the processing circuitry suppresses the at least one response action and stores elements identifying information identifying which data element is the given active data element which triggered the exceptional condition. This can be useful for reducing the amount of hardware resource for tracking the occurrence of the exceptional conditions and/or supporting speculative execution of vector instructions.

公开(公告)号：US20180203756A1

公开(公告)日：2018-07-19

申请号：US15743392

申请日：2016-06-21

Applicant: ARM LIMITED

Inventor： Nigel John STEPHENS ,  Michael John WILLIAMS ,  Richard Roy GRISENTHWAITE

IPC: G06F11/07 ,  G06F9/30

CPC classification number: G06F11/079 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/3865 ,  G06F11/0721 ,  G06F11/0751 ,  G06F11/0793

Abstract: A data processing system (2) supports non-speculative execution of vector load instructions that perform at least one contingent load of a data value. Fault detection circuitry (26) serves to detect whether a contingent load is fault-generating contingent load or a fault-free contingent load. Contingent load suppression circuitry (28) detects and suppresses a fault-free contingent load that matches a predetermined criteria that may result in an undesired change of architectural state (undesired side-effect). Examples of such predetermined criteria are that the contingent load is to a non-memory device or that the contingent load will trigger a diagnostic response such as entry of a halting debug halting mode or triggering of a debug exception.

公开(公告)号：US20170031865A1

公开(公告)日：2017-02-02

申请号：US14814590

申请日：2015-07-31

Applicant: ARM LIMITED ,  APPLE, INC.

Inventor： Mbou EYOLE ,  Nigel John STEPHENS ,  Jeffry GONION ,  Alex KLAIBER ,  Charles TUCKER

IPC: G06F15/80 ,  G06F9/30

CPC classification number: G06F15/8076 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30192 ,  G06F9/345 ,  G06F9/3455 ,  G06F9/355 ,  G06F9/3887

Abstract: An apparatus and method are provided for transferring a plurality of data structures between memory and a plurality of vector registers, each vector register being arranged to store a vector operand comprising a plurality of data elements. Access circuitry is used to perform access operations to move data elements of vector operands between the data structures in memory and specified vector registers, each data structure comprising multiple data elements stored at contiguous addresses in the memory. Decode circuitry is responsive to a single access instruction identifying a plurality of vector registers and a plurality of data structures that are located discontiguously with respect to each other in the memory, to generate control signals to control the access circuitry to perform a sequence of access operations to move the plurality of data structures between the memory and the plurality of vector registers such that the vector operand in each vector register holds a corresponding data element from each of the plurality of data structures. This provides a very efficient mechanism for performing complex access operations, resulting in an increase in execution speed, and potential reductions in power consumption.

Abstract translation: 提供了一种用于在存储器和多个向量寄存器之间传送多个数据结构的装置和方法，每个向量寄存器被布置为存储包括多个数据元素的向量操作数。 访问电路用于执行访问操作以在存储器和指定向量寄存器中的数据结构之间移动向量操作数的数据元素，每个数据结构包括存储在存储器中的连续地址处的多个数据元素。 解码电路响应于识别多个向量寄存器的单个访问指令和在存储器中相对于彼此无关位置的多个数据结构，以产生控制信号以控制访问电路执行一系列访问操作 以在存储器和多个向量寄存器之间移动多个数据结构，使得每个向量寄存器中的向量操作数保持来自多个数据结构中的每一个的相应数据元素。 这为执行复杂的访问操作提供了非常有效的机制，从而导致执行速度的提高以及潜在的功耗降低。

公开(公告)号：US20210042115A1

公开(公告)日：2021-02-11

申请号：US16531208

申请日：2019-08-05

Applicant: Arm Limited

Inventor： Nigel John STEPHENS ,  David Hennah MANSELL ,  Richard Roy GRISENTHWAITE ,  Matthew Lucien EVANS

IPC: G06F9/30

Abstract: An apparatus comprises: an instruction decoder and processing circuitry. In response to a data structure processing instruction specifying at least one input data structure identifier and an output data structure identifier, the instruction decoder controls the processing circuitry to perform a processing operation on at least one input data structure to generate an output data structure. Each input/output data structure comprises an arrangement of data corresponding to a plurality of memory addresses. The apparatus comprises two or more sets of one or more data structure metadata registers, each set associated with a corresponding data structure identifier and designated to store address-indicating metadata for identifying the memory addresses for the data structure identified by the corresponding data structure identifier.

公开(公告)号：US20200225953A1

公开(公告)日：2020-07-16

申请号：US16629178

申请日：2018-06-27

Applicant: ARM LIMITED

Inventor： Grigorios MAGKLIS ,  Nigel John STEPHENS

IPC: G06F9/30

Abstract: An apparatus and method of operating an apparatus are provided. The apparatus is responsive to a bit-testing instruction which specifies a source vector register and an index to perform a bit-testing procedure on plural elements stored in the source vector register to generate plural result bits. The bit-testing procedure comprises, for each processed element of the plural elements, setting a respective result bit of the plural result bits in dependence on a value of a tested bit at a bit position in the processed element of the source vector register indicated by the index. This bit-testing instruction thus enables increased performance of program code which is required to perform multiple bit tests and can be suitably formulated into a vectorised form.

公开(公告)号：US20190171376A1

公开(公告)日：2019-06-06

申请号：US16309190

申请日：2017-05-18

Applicant: ARM LIMITED

Inventor： Nigel John STEPHENS ,  Grigorios MAGKLIS

IPC: G06F3/06 ,  G06F12/10 ,  G06F9/30

Abstract: A data processing apparatus and method serve to manage access permission checking in respect of contingent memory access operations (the access permission failure of which does not alter program flow) in dependence of a contingent-access permission checking disable flag. If the contingent access disable flag has a first value, then this disables memory permission circuitry e.g. a walk state machine 22, from performing a check as to whether or not the memory access circuitry is permitted to perform a requested memory access. Non-contingent memory accesses are able to utilise the memory permission circuitry irrespective of the value of the contingent-access permission checking disable flag.