公开(公告)号：US20190146693A1

公开(公告)日：2019-05-16

申请号：US16170371

申请日：2018-10-25

Applicant: Arm Limited

Inventor： Christopher Vincent SEVERINO ,  Seow Chuan LIM ,  Aris Doros ARISTODEMOU ,  Matthew Lucien EVANS

IPC: G06F3/06 ,  G06F12/14

Abstract: There is provided an apparatus for receiving a request from a master to access an input address. Coarse grain access circuitry stores and provides a reference to an area of an output address space in dependence on the input address. One or more fine grain access circuits, each store and provide a reference to a sub-area in the area of the output address space in dependence on the input address. The apparatus forwards the request from the coarse grain access circuitry to one of the one fine grain access circuits in dependence on the input address.

公开(公告)号：US20220283847A1

公开(公告)日：2022-09-08

申请号：US17190729

申请日：2021-03-03

Applicant: Arm Limited

Inventor： Håkan Lars-Göran PERSSON ,  Frederic Claude Marie PIRY ,  Matthew Lucien EVANS ,  Albin Pierrick TONNERRE

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/30 ,  G06F12/10

Abstract: Apparatuses and methods are disclosed for performing data processing operations in main processing circuitry and delegating certain tasks to auxiliary processing circuitry. User-specified instructions executed by the main processing circuitry comprise a task dispatch specification specifying an indication of the auxiliary processing circuitry and multiple data words defining a delegated task comprising at least one virtual address indicator. In response to the task dispatch specification the main processing circuitry performs virtual-to-physical address translation with respect to the at least one virtual address indicator to derive at least one physical address indicator, and issues a task dispatch memory write transaction to the auxiliary processing circuitry comprises the indication of the auxiliary processing circuitry and the multiple data words, wherein the at least one virtual address indicator in the multiple data words is substituted by the at least one physical address indicator.

公开(公告)号：US20210042115A1

公开(公告)日：2021-02-11

申请号：US16531208

申请日：2019-08-05

Applicant: Arm Limited

Inventor： Nigel John STEPHENS ,  David Hennah MANSELL ,  Richard Roy GRISENTHWAITE ,  Matthew Lucien EVANS

IPC: G06F9/30

Abstract: An apparatus comprises: an instruction decoder and processing circuitry. In response to a data structure processing instruction specifying at least one input data structure identifier and an output data structure identifier, the instruction decoder controls the processing circuitry to perform a processing operation on at least one input data structure to generate an output data structure. Each input/output data structure comprises an arrangement of data corresponding to a plurality of memory addresses. The apparatus comprises two or more sets of one or more data structure metadata registers, each set associated with a corresponding data structure identifier and designated to store address-indicating metadata for identifying the memory addresses for the data structure identified by the corresponding data structure identifier.

公开(公告)号：US20180357178A1

公开(公告)日：2018-12-13

申请号：US15620017

申请日：2017-06-12

Applicant: ARM LIMITED

Inventor： Bruce James MATHEWSON ,  Phanindra Kumar MANNAVA ,  Matthew Lucien EVANS ,  Paul Gilbert MEYER ,  Andrew Brookfield SWAINE

IPC: G06F12/1036 ,  G06F12/0802 ,  G06F12/14 ,  G06F13/16

CPC classification number: G06F12/1036 ,  G06F12/0802 ,  G06F12/1425 ,  G06F13/1668

Abstract: Access control circuitry comprises: a detector to detect a memory address translation between a virtual memory address in a virtual memory address space and a physical memory address in a physical memory address space, provided in response to a translation request by further circuitry; an address translation memory, to store data representing a set of physical memory addresses previously provided to the further circuitry in response to translation requests by the further circuitry; an interface to receive a physical memory address from the further circuitry for a memory access by the further circuitry; a comparator to compare a physical memory address received from the further circuitry with the set of physical addresses stored by the address translation memory, and to permit access, by the further circuitry, to a physical address included in the set of one or more physical memory addresses.

公开(公告)号：US20180150413A1

公开(公告)日：2018-05-31

申请号：US15578340

申请日：2016-04-26

Applicant: ARM LIMITED

Inventor： Jason PARKER ,  Richard Roy GRISENTHWAITE ,  Andrew Christopher ROSE ,  Matthew Lucien EVANS

IPC: G06F12/14 ,  G06F9/50 ,  G06F9/46 ,  G06F9/48 ,  G06F12/02 ,  G06F11/07 ,  G06F9/455

Abstract: A data processing system for processing data comprising: ownership circuitry to enforce ownership rights of memory regions, a given more privileged state memory region having a given owning process specified from among a plurality of processes, said given owning process having exclusive rights to control access to said given memory region; and context switching circuitry responsive to receipt of an interrupt to trigger a context switch from a first active process to a second active process whereby one or more items of state for use in restarting said first process is saved to one or more context data memory regions owned by said first process and one or more items of state accessible to said second process and dependent upon processing by said first process is overwritten prior to commencing execution of said second process.

公开(公告)号：US20140351471A1

公开(公告)日：2014-11-27

申请号：US13898816

申请日：2013-05-21

Applicant: ARM LIMITED

Inventor： Anthony JEBSON ,  Andrew John TURNER ,  Matthew Lucien EVANS ,  Gareth James EVANS ,  Adam James MCNEENEY

IPC: G06F13/24

CPC classification number: G06F13/24 ,  G06F9/45533 ,  G06F9/4812

Abstract: An interrupt controller for controlling the routing and handling of interrupts received at a data processing apparatus including at least one physical processing unit configured to run at least one of a plurality of virtual processors and a memory. The interrupt controller includes redistribution circuitry with at least one data store corresponding to the unit, the data store storing a pointer to a virtual pending table storing currently pending virtual interrupts for a virtual processor currently running on the corresponding unit and a pointer to a pending table configured to store currently pending physical interrupts for the corresponding unit and an input configured to receive a virtual interrupt for interrupting a virtual processor. Control circuitry is configured to add the virtual interrupt to the virtual pending table and to store the virtual interrupt in the virtual pending table for the virtual processor that is stored in the memory.

Abstract translation: 一种中断控制器，用于控制在包括至少一个物理处理单元的数据处理装置处接收的中断的路由和处理，所述物理处理单元被配置为运行多个虚拟处理器和存储器中的至少一个。 中断控制器包括具有与单元对应的至少一个数据存储器的再分配电路，数据存储器存储指向虚拟挂起表的指针，该虚拟挂起表存储当前在相应单元上运行的虚拟处理器的当前待处理的虚拟中断，以及指向待处理表的指针 被配置为存储用于相应单元的当前待处理的物理中断，以及被配置为接收用于中断虚拟处理器的虚拟中断的输入。 控制电路被配置为将虚拟中断添加到虚拟挂起表并将虚拟中断存储在存储在存储器中的虚拟处理器的虚拟挂起表中。

公开(公告)号：US20210365386A1

公开(公告)日：2021-11-25

申请号：US17395840

申请日：2021-08-06

Applicant: Arm Limited

Inventor： Matthew Lucien EVANS

IPC: G06F12/1036

Abstract: A memory management unit comprises an interface for receiving an address translation request from a device, the address translation request specifying a virtual request to be translated. Translation circuitry translates the virtual address into an intermediate address different from a physical address directly specifying a memory location. The interface provides an address translation response specifying the intermediate address to the device in response to the address translation request. This improves security by avoiding exposure of physical addresses to the device.

公开(公告)号：US20200242047A1

公开(公告)日：2020-07-30

申请号：US16756288

申请日：2018-10-11

Applicant: Arm Limited

Inventor： Matthew Lucien EVANS

IPC: G06F12/1009 ,  G06F16/22 ,  G06F9/455

Abstract: A method for locating metadata associated with a first address. The method comprises: accessing a page table structure, a page table entry of said page table structure providing address translation data for use in an address translation process for translating said first address into a second address; extracting (906) portions of at least two page table entries in the page table structure, determining (906) a pointer to a metadata table from said portions, and using (908) the pointer to locate from the metadata table target metadata associated with the first address.

公开(公告)号：US20200226061A1

公开(公告)日：2020-07-16

申请号：US16647659

申请日：2018-10-11

Applicant: ARM Limited

Inventor： Jason PARKER ,  Djordje KOVACEVIC ,  Gareth Rhys STOCKWELL ,  Matthew Lucien EVANS

IPC: G06F12/02 ,  G06F12/14

Abstract: A realm management unit (RMU) 20 manages ownership of memory regions by realms, each realm corresponding to at least a portion of a software process executed by processing circuitry. Memory access circuitry 26 enforces ownership rights for the regions, with the owner realm having a right to exclude other realms from accessing data stored within its owned region. The RMU 20 controls transitions of memory regions between region states, including an invalid state 220, a valid state 222, and a scrub-commit state 800 in which the memory region is allocated to an owner realm, inaccessible to that owner realm until a scrubbing process has been performed for the memory region to set each storage location of the region to a value uncorrelated with a previous value stored in the storage location, and prevented from being reallocated to a different owner realm.

公开(公告)号：US20160085669A1

公开(公告)日：2016-03-24

申请号：US14494000

申请日：2014-09-23

Applicant: ARM Limited

Inventor： Ali Ghassan SAIDI ,  Aniruddha Nagendran UDIPI ,  Matthew Lucien EVANS ,  Geoffrey BLAKE ,  Robert Gwilym DIMOND

IPC: G06F12/02 ,  G06F12/10

CPC classification number: G06F12/1027 ,  G06F2212/654 ,  G06F2212/681

Abstract: A data processing system utilising a descriptor ring 24 to facilitate communication between one or more general purpose processors 4, 6 and one or more devices 20, 22 employs a system memory management unit 18 for managing access by the devices 20, 22 to a main memory 16. The system memory management unit 18 uses address translation data for translating memory addresses generated by the devices 20, 22 into addresses supplied to the main memory 16. Prefetching circuitry 38 within the system memory management unit 18 serves to detect pointers read from the descriptor ring 24 and to prefetch address translation data into the translation lookaside buffer 30 of the system memory management unit 18.

Abstract translation: 使用描述符环24以促进一个或多个通用处理器4,6与一个或多个设备20,22之间的通信的数据处理系统使用系统存储器管理单元18，用于管理设备20,22对主存储器的访问 系统存储器管理单元18使用地址转换数据将由设备20,22产生的存储器地址转换成提供给主存储器16的地址。系统存储器管理单元18内的预取电路38用于检测从描述符读取的指针 并且将地址转换数据预取到系统存储器管理单元18的翻译后备缓冲器30中。