公开(公告)号：US09910824B2

公开(公告)日：2018-03-06

申请号：US14727076

申请日：2015-06-01

申请人： Optimum Semiconductor Technologies, Inc.

发明人： Mayan Moudgill ,  Gary J. Nacer ,  C. John Glossner ,  Arthur Joseph Hoane ,  Paul Hurtley ,  Murugappan Senthilvelan ,  Pablo Balzola

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F15/80 ,  G06F15/78 ,  G06F17/14

CPC分类号： G06F15/8053 ,  G06F9/3001 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30141 ,  G06F9/3836 ,  G06F9/3855 ,  G06F15/7828 ,  G06F15/7839 ,  G06F15/8076 ,  G06F17/142

摘要： A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising at least one register to hold a varying number of elements. The computer processor may further comprise processing logic configured to operate on the varying number of elements in the vector register file using one or more instructions that separate a vector or combine two vectors. The computer processor may be implemented as a monolithic integrated circuit.

公开(公告)号：US09870340B2

公开(公告)日：2018-01-16

申请号：US14672568

申请日：2015-03-30

申请人： International Business Machines Corporation

发明人： Constantinos Evangelinos ,  Changhoan Kim ,  Ravi Nair

IPC分类号： G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/80 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38

CPC分类号： G06F15/8076 ,  G06F9/30036 ,  G06F9/30189 ,  G06F9/321 ,  G06F9/3851 ,  G06F15/8053 ,  G06F15/8084

摘要： In one embodiment, a system includes a processor having a vector processing mode and a multithreading mode. The processor is configured to operate on one thread per cycle in the multithreading mode. The processor includes a program counter register having a plurality of program counters, and the program counter register is vectorized. Each program counter in the program counter register represents a distinct corresponding thread of a plurality of threads. The processor is configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle.

公开(公告)号：US09606921B2

公开(公告)日：2017-03-28

申请号：US14337045

申请日：2014-07-21

申请人： Oracle International Corporation

发明人： Jesse Kamp ,  Vineet Marwah ,  Amit Ganesh ,  Michael Gleeson ,  Maheswaran Venkatachalam ,  Allison Holloway ,  Niloy Mukherjee ,  Sanket Hase

IPC分类号： G06F17/30 ,  G06F12/0815 ,  G06F15/78 ,  G06F12/1018 ,  G06F3/06

CPC分类号： G06F17/30315 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/065 ,  G06F3/0689 ,  G06F12/0815 ,  G06F12/1018 ,  G06F15/78 ,  G06F15/8007 ,  G06F15/8076 ,  G06F15/8084 ,  G06F17/30312 ,  G06F17/30377 ,  G06F17/30477 ,  G06F17/30595 ,  G06F2003/0697 ,  G06F2212/1021 ,  G06F2212/1032 ,  G06F2212/2542 ,  G06F2212/313

摘要： Techniques are provided for granular load and refresh of columnar data. In an embodiment, a particular data object that contains particular data formatted different from column-major format is maintained, the particular data including first data and second data. First and second data objects contain the first and second data, respectively, organized in the column-major format. In response to changes being committed to the first data in the particular data object, invalidating one or more rows of the first data object. In response to a number of invalidated rows of the first data object exceeding a threshold, automatically performing a refresh operation on the first data object independent of any refresh operation on the second data object.

公开(公告)号：US09600282B2

公开(公告)日：2017-03-21

申请号：US14724995

申请日：2015-05-29

申请人： International Business Machines Corporation

发明人： Michael K. Gschwind ,  Brett Olsson

IPC分类号： G06F9/30 ,  G06F15/80

CPC分类号： G06F9/30043 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30185 ,  G06F9/30189 ,  G06F15/8061 ,  G06F15/8076

摘要： Embodiments relate to vector processors. An aspect includes endian-mode-sensitive memory instructions for a vector processor. One embodiment includes a computer-implemented method for copying data between a vector register that includes byte elements 0 to S and a memory that is byte addressable. The computer-implemented method includes obtaining a vector instruction by a processor in a computer. The processor determines that the vector instruction is a memory access instruction specifying the vector register and a memory address. In response to the determination that is instruction is a memory access instruction and independent of a current global endian mode setting that is selectable in the processor, the processor executes the memory access instruction by copying the byte data between the memory and the vector register so that the byte element n of the vector register corresponds to the memory address+n for n=0 to S.

公开(公告)号：US20150248291A1

公开(公告)日：2015-09-03

申请号：US14193491

申请日：2014-02-28

申请人： International Business Machines Corporation

发明人： Michael K. Gschwind ,  Brett Olsson

IPC分类号： G06F9/30

CPC分类号： G06F9/30043 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30185 ,  G06F9/30189 ,  G06F15/8061 ,  G06F15/8076

摘要： An aspect includes implementing endian-mode-sensitive memory instructions for a vector processor. One such system includes a byte addressable memory and a processor. The processor includes a register that includes a plurality of byte elements 0 to S. The system is configured to perform a method that includes obtaining an instruction by the processor and determining that the instruction is a memory access instruction specifying the register and a memory address. In response to the determination that the instruction is a memory access instruction and independent of a current global endian mode setting that is selectable in the processor, the memory access instruction is executed by copying the byte data between the memory and the register so that the byte element n of the register corresponds to the memory address+n for n=0 to S.

摘要翻译： 一个方面包括为矢量处理器实现端模式敏感存储器指令。 一个这样的系统包括字节可寻址存储器和处理器。 处理器包括一个包括多个字节元素0至S的寄存器。该系统被配置为执行一种方法，该方法包括获得处理器的指令，并确定该指令是指定寄存器的存储器访问指令和存储器地址。 响应于指令是存储器访问指令并且独立于在处理器中可选择的当前全局端模式设置的确定，通过在存储器和寄存器之间复制字节数据来执行存储器访问指令，使得字节 寄存器的元素n对应于n = 0到S的存储器地址+ n。

公开(公告)号：US20140047211A1

公开(公告)日：2014-02-13

申请号：US13572886

申请日：2012-08-13

申请人： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

发明人： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC分类号： G06F15/76

CPC分类号： G06F15/8076 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30109 ,  G06F9/34 ,  G06F9/345

摘要： An aspect includes accessing a vector register in a vector register file. The vector register file includes a plurality of vector registers and each vector register includes a plurality of elements. A read command is received at a read port of the vector register file. The read command specifies a vector register address. The vector register address is decoded by an address decoder to determine a selected vector register of the vector register file. An element address is determined for one of the plurality of elements associated with the selected vector register based on a read element counter of the selected vector register. A word is selected in a memory array of the selected vector register as read data based on the element address. The read data is output from the selected vector register based on the decoding of the vector register address by the address decoder.

摘要翻译： 一个方面包括访问向量寄存器文件中的向量寄存器。 向量寄存器文件包括多个向量寄存器，并且每个向量寄存器包括多个元素。 在向量寄存器文件的读端口处接收到读命令。 读命令指定向量寄存器地址。 向量寄存器地址由地址解码器解码，以确定向量寄存器文件的选定向量寄存器。 基于所选择的向量寄存器的读元素计数器，确定与所选向量寄存器相关联的多个元素之一的元素地址。 在所选向量寄存器的存储器阵列中选择一个字作为基于元素地址的读取数据。 基于由地址解码器对向量寄存器地址的解码，从所选向量寄存器输出读取数据。

公开(公告)号：US20120284487A1

公开(公告)日：2012-11-08

申请号：US13462144

申请日：2012-05-02

申请人： Anindya SAHA ,  Gururaj PADAKI ,  Santosh BILLAVA ,  Rakesh A. JOSHI

发明人： Anindya SAHA ,  Gururaj PADAKI ,  Santosh BILLAVA ,  Rakesh A. JOSHI

IPC分类号： G06F15/76 ,  G06F9/302

CPC分类号： G06F9/3887 ,  G06F7/552 ,  G06F7/586 ,  G06F9/3001 ,  G06F9/30109 ,  G06F9/3893 ,  G06F15/8053 ,  G06F15/8076 ,  G06F2207/3828 ,  G06F2207/5523 ,  H04L25/03019 ,  H04L27/0008

摘要： A vector slot processor that is capable of supporting multiple signal processing operations for multiple demodulation standards is provided. The vector slot processor includes a plurality of micro execution slot (MES) that performs the multiple signal processing operations on the high speed streaming inputs. Each of the MES includes one or more n-way signal registers that receive the high speed streaming inputs, one or more n-way coefficient registers that store filter coefficients for the multiple signal processing, and one or more n-way Multiply and Accumulate (MAC) units that receive the high speed streaming inputs from the one or more n-way signal registers and filter coefficients from one or more n-way coefficient registers. The one or more n-way MAC units perform a vertical MAC operation and a horizontal multiply and add operation on the high speed streaming inputs.

摘要翻译： 提供了能够支持用于多个解调标准的多个信号处理操作的向量时隙处理器。 矢量时隙处理器包括对高速流输入进行多信号处理操作的多个微执行时隙（MES）。 每个MES包括接收高速流输入的一个或多个n路信号寄存器，存储多信号处理的滤波器系数的一个或多个n路系数寄存器和一个或多个n路乘法和累加（ MAC）单元，其从一个或多个n路信号寄存器接收高速流输入和来自一个或多个n路系数寄存器的滤波器系数。 一个或多个n路MAC单元在高速流输入上执行垂直MAC操作和水平乘法和相加操作。

公开(公告)号：US20120173864A1

公开(公告)日：2012-07-05

申请号：US13342157

申请日：2012-01-02

申请人： Dominik J. Schmidt ,  Robert Warren Sherburne, JR.

发明人： Dominik J. Schmidt ,  Robert Warren Sherburne, JR.

IPC分类号： G06F9/06

CPC分类号： G06F9/3887 ,  G06F9/30036 ,  G06F9/3877 ,  G06F9/3897 ,  G06F15/8076 ,  H04M2201/34

摘要： A processor includes a scalar computation unit; a vector co-processor coupled to the scalar computation unit; and one or more function-specific engines coupled to the scalar computation unit, the engines adapted to minimize data exchange penalties by processing small in-out bit slices.

摘要翻译： 处理器包括标量计算单元; 耦合到标量计算单元的矢量协处理器; 以及耦合到标量计算单元的一个或多个功能特定引擎，发动机适于通过处理小的进出位片来最小化数据交换惩罚。

公开(公告)号：US20100106939A1

公开(公告)日：2010-04-29

申请号：US12258465

申请日：2008-10-27

申请人： Daniel Citron ,  Ayal Zaks

发明人： Daniel Citron ,  Ayal Zaks

IPC分类号： G06F15/76 ,  G06F9/315

CPC分类号： G06F9/30098 ,  G06F9/30025 ,  G06F9/30036 ,  G06F15/8076

摘要： A method for transferring data from a general purpose register to a vector register, the method including splatting a byte of data directly from a general purpose register (GPR) to a vector register (VR) by means of vector permute instructions, and splatting another byte of data from the GPR to the VR and vectorially combining the data in the VR.

摘要翻译： 一种用于将数据从通用寄存器传送到向量寄存器的方法，所述方法包括通过向量置换指令直接从通用寄存器（GPR）向矢量寄存器（VR）直接分割数据字节，以及分割另一字节 的数据从GPR到VR并且在VR中的数据进行矢量组合。

公开(公告)号：US20100017450A1

公开(公告)日：2010-01-21

申请号：US12400572

申请日：2009-03-09

申请人： Yanmeng Sun ,  Liangliang Hu

发明人： Yanmeng Sun ,  Liangliang Hu

IPC分类号： G06F17/14 ,  G06F17/16

CPC分类号： G06F15/8061 ,  G06F7/785 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30134 ,  G06F15/8076 ,  G06F17/16

摘要： A system and method for vector memory array transposition. The system includes a vector memory, a block transposition accelerator, and an address controller. The vector memory stores a vector memory array. The block transposition accelerator reads a vector of a block of data within the vector memory array. The block transposition accelerator also writes a transposition of the vector of the block of data to the vector memory. The address controller determines a vector access order, and the block transposition accelerator accesses the vector of the block of data within the vector memory array according to the vector access order.

摘要翻译： 一种用于向量存储器阵列转置的系统和方法。 该系统包括向量存储器，块转置加速器和地址控制器。 矢量存储器存储向量存储器阵列。 块转置加速器读取向量存储器阵列内的数据块的向量。 块转置加速器还将数据块向量的转置写入向量存储器。 地址控制器确定向量访问顺序，并且块转置加速器根据向量存取顺序访问向量存储器阵列内的数据块的向量。