公开(公告)号：US20200312403A1

公开(公告)日：2020-10-01

申请号：US16368246

申请日：2019-03-28

Applicant: Arm Limited

Inventor： Ankur Goel ,  Ishan Khera ,  Nimish Sharma ,  Ishita Satishchandra Desai ,  Vikash Kumar ,  Nitesh Gautam

IPC: G11C11/419

Abstract: Briefly, embodiments of claimed subject matter relate to circuits and/or methods, which operate to introduce a variable delay in a write-assist signal to a write driver of an array of SRAM cells. In particular embodiments, a variable delay may be introduced by way of a voltage tracking circuit, which may generate a trigger signal in response to a voltage signal from an array of access devices that replicate access devices of the array of SRAM cells.

公开(公告)号：US12159664B2

公开(公告)日：2024-12-03

申请号：US16709665

申请日：2019-12-10

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Bo Zheng ,  Fakhruddin Ali Bohra ,  Nimish Sharma ,  Nicolaas Klarinus Johannes Van Winkelhoff ,  El Mehdi Boujamaa

IPC: G11C11/419 ,  G11C11/16

Abstract: Various implementations described herein refer to a method for providing memory with one or more banks. The method may include coupling read-write column multiplexer circuitry to the memory via bitlines including coupling a write column multiplexer to the bitlines for write operations and coupling a read column multiplexer to the bitlines for read operations. The method may include performing concurrent read operations and write operations in the one or more banks of the memory with the write column multiplexer and the read column multiplexer via the bitlines.

公开(公告)号：US20210158865A1

公开(公告)日：2021-05-27

申请号：US16698866

申请日：2019-11-27

Applicant: Arm Limited

Inventor： Lalit Gupta ,  El Mehdi Boujamaa ,  Nicolaas Klarinus Johannes VAN WINKELHOFF ,  Bo Zheng ,  Fakhruddin Ali Bohra ,  Nimish Sharma ,  Hetansh Pareshbhai Shah

IPC: G11C11/419 ,  G11C11/16 ,  G11C11/418

Abstract: Various implementations described herein are directed to a device having memory circuitry with a core array of bitcells. The device may include write assist circuitry having passgates coupled to the bitcells via bitlines. The passgates may include a first passgate coupled to the bitcells via a first bitline and a second passgate coupled to the bitcells via a second bitline, and a gate of the second passgate may be coupled to the first bitline.

公开(公告)号：US11004503B1

公开(公告)日：2021-05-11

申请号：US16698866

申请日：2019-11-27

Applicant: Arm Limited

Inventor： Lalit Gupta ,  El Mehdi Boujamaa ,  Nicolaas Klarinus Johannes Van Winkelhoff ,  Bo Zheng ,  Fakhruddin Ali Bohra ,  Nimish Sharma ,  Hetansh Pareshbhai Shah

IPC: G11C11/419 ,  G11C11/16 ,  G11C11/418

Abstract: Various implementations described herein are directed to a device having memory circuitry with a core array of bitcells. The device may include write assist circuitry having passgates coupled to the bitcells via bitlines. The passgates may include a first passgate coupled to the bitcells via a first bitline and a second passgate coupled to the bitcells via a second bitline, and a gate of the second passgate may be coupled to the first bitline.

公开(公告)号：US11574660B2

公开(公告)日：2023-02-07

申请号：US16989883

申请日：2020-08-11

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Nimish Sharma ,  Hetansh Pareshbhai Shah ,  Bo Zheng

IPC: G11C7/10 ,  G11C7/06 ,  G11C16/26 ,  G11C16/10

Abstract: In a particular implementation, a circuit comprises: a memory array including a plurality of bit cells, where each of the bit cells are coupled to a respective bit path; a first multiplexer comprising a plurality of column address locations, where each of the plurality of column address locations is coupled to the memory array and corresponds to a respective bit path capacitance; and a variable capacitance circuit coupled to a reference path and configured to substantially match reference path capacitance to each of the respective bit path capacitances.

公开(公告)号：US20210110867A1

公开(公告)日：2021-04-15

申请号：US16709665

申请日：2019-12-10

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Bo Zheng ,  Fakhruddin Ali Bohra ,  Nimish Sharma ,  Nicolaas Klarinus Johannes Van Winkelhoff ,  El Mehdi Boujamaa

IPC: G11C11/419 ,  G11C11/16

Abstract: Various implementations described herein refer to a method for providing memory with one or more banks. The method may include coupling read-write column multiplexer circuitry to the memory via bitlines including coupling a write column multiplexer to the bitlines for write operations and coupling a read column multiplexer to the bitlines for read operations. The method may include performing concurrent read operations and write operations in the one or more banks of the memory with the write column multiplexer and the read column multiplexer via the bitlines.

公开(公告)号：US10861534B2

公开(公告)日：2020-12-08

申请号：US16368246

申请日：2019-03-28

Applicant: Arm Limited

Inventor： Ankur Goel ,  Ishan Khera ,  Nimish Sharma ,  Ishita Satishchandra Desai ,  Vikash Kumar ,  Nitesh Gautam

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412 ,  H01L27/11 ,  G11C11/413

Abstract: The claimed subject matter relate to circuits and/or methods, which operate to introduce a variable delay in a write-assist signal to a write driver of an array of SRAM cells. Particularly, a variable delay may be introduced by way of a voltage tracking circuit, which may generate a trigger signal in response to a voltage signal from an array of access devices that replicate access devices of the array of SRAM cells.