公开(公告)号：US20210091041A1

公开(公告)日：2021-03-25

申请号：US16580349

申请日：2019-09-24

Applicant: Arm Limited

Inventor： Saurabh Pijuskumar SINHA ,  Joel Thornton IRBY ,  Supreet JELOKA

IPC: H01L25/065 ,  H01L23/367 ,  H01L21/66 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00

Abstract: A three-dimensional (3D) integrated circuit (IC) can include a bottom tier with first circuitry and first backside TSVs coupled to a substrate; a top tier coupled to the first tier at a front side and having second circuitry and second backside TSVs; and a heat conductor on the second backside TSVs of the top tier. The heat conductor is coupled to the second backside TSVs to provide improved heat dissipation through the top tier. During pre-bond testing, the top tier can be tested at speed using the second backside TSVs.

公开(公告)号：US20240036923A1

公开(公告)日：2024-02-01

申请号：US17874658

申请日：2022-07-27

Applicant: Arm Limited

Inventor： Rishav ROY ,  Supreet JELOKA ,  Shidhartha DAS ,  Rahul MATHUR

IPC: G06F9/48

CPC classification number: G06F9/4893

Abstract: Aspects of the present disclosure relate to an apparatus comprising a plurality of processing elements having a spatial layout, and control circuitry to assign workloads to said plurality of processing elements. The control circuitry is configured to, based on a timing parameter, determine one or more active processing elements to deactivate; determine, based on the spatial layout, one or more inactive processing elements to activate; and deactivate said one or more active processing elements and activate said one or more inactive processing elements.

公开(公告)号：US20220035679A1

公开(公告)日：2022-02-03

申请号：US16943117

申请日：2020-07-30

Applicant: Arm Limited

Inventor： Dam SUNWOO ,  Supreet JELOKA ,  Saurabh Pijuskumar SINHA ,  Jaekyu LEE ,  Jose Alberto JOAO ,  Krishnendra NATHELLA

IPC: G06F9/50 ,  G06N20/00 ,  G06N5/04

Abstract: A method for controlling hardware resource configuration for a processing system comprises obtaining performance monitoring data indicative of processing performance associated with workloads to be executed on the processing system, providing a trained machine learning model with input data depending on the performance monitoring data; and based on an inference made from the input data by the trained machine learning model, setting control information for configuring the processing system to control an amount of hardware resource allocated for use by at least one processor core. A corresponding method of training the model is provided. This is particularly useful for controlling inter-core borrowing of resource between processor cores in a multi-core processing system, where resource is borrowed between respective cores, e.g. cores on different layers of a 3D integrated circuit.