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    LOCKSTEP PROCESSING SYSTEMS AND METHODS
    2.
    发明申请
    LOCKSTEP PROCESSING SYSTEMS AND METHODS 审中-公开

    公开(公告)号：US20190370130A1

    公开(公告)日：2019-12-05

    申请号：US15995469

    申请日：2018-06-01

    Applicant: Arm Limited

    Inventor： Milosch MERIAC ,  Shidhartha DAS

    IPC: G06F11/16 ,  G06F1/12

    Abstract: The present techniques generally relate to a method of monitoring for a fault event in a lockstep processing system having a plurality of cores configured to operate in lockstep, the method having: power gating, for a period of time, a subset of cores of the plurality of cores from a first power source and providing power to the subset of cores from a second power source for the period of time; processing, at each of the cores of the plurality of cores, one or more instructions; providing an output from each core of the plurality of cores to error detection circuitry to monitor for the fault event, the output from each core based on or in response to processing the one or more instructions during the period of time.

    POWER ANALYSIS
    5.
    发明申请
    POWER ANALYSIS 审中-公开

    公开(公告)号：US20190064896A1

    公开(公告)日：2019-02-28

    申请号：US15692282

    申请日：2017-08-31

    Applicant: ARM Limited ,  University of Cyprus

    Inventor： Zachharias Hadjilambrou DAS ,  Shidhartha DAS ,  Yanos SAZEIDES

    IPC: G06F1/26 ,  G05F1/70

    Abstract: A power analysis apparatus includes antenna circuitry gathers readings of electromagnetic waves that emanate from a power delivery network of a circuit to be analysed. Spectral analysis circuitry analyses the readings to determine a resonance frequency from said electromagnetic waves and processing circuitry performs one or more actions based on the resonance frequency.

    CIRCUIT DELAY MONITORING APPARATUS AND METHOD
    6.
    发明申请
    CIRCUIT DELAY MONITORING APPARATUS AND METHOD 有权
    电路延时监控装置及方法

    公开(公告)号：US20150137864A1

    公开(公告)日：2015-05-21

    申请号：US14081900

    申请日：2013-11-15

    Applicant: ARM Limited

    Inventor： Paul Nicholas WHATMOUGH ,  Shidhartha DAS ,  David Michael BULL

    IPC: H03K5/135

    CPC classification number: H03K5/135

    Abstract: A circuit delay monitoring apparatus has a ring oscillator with a plurality of delay elements, a signal transition being propagated through the delay elements of the ring oscillator, and a plurality N of sampling points being distributed around the ring oscillator. Selection circuitry selects, in dependence on the indication of the current location of the signal transition generated by the fine sampling circuitry, one of the M transition counter circuits whose associated location is greater than said predetermined amount from the current location of the signal transition. Output generation circuitry then generates a count indication for a reference time period dependent on a sampled count value of the transition counter circuit selected by the selection circuitry, the indication of the current location of the signal transition within the ring oscillator, and reference count data relating to the start of the reference time period.

    Abstract translation: 电路延迟监视装置具有环形振荡器，具有多个延迟元件，信号转换通过环形振荡器的延迟元件传播，并且多个采样点分布在环形振荡器周围。 选择电路根据由精细采样电路产生的信号转换的当前位置的指示来选择M个转换计数器电路中的一个，其相关位置大于来自信号转换的当前位置的所述预定量。 输出产生电路然后根据由选择电路选择的转换计数器电路的采样计数值，环形振荡器内的信号转换的当前位置的指示以及相关的参考计数数据，生成参考时间段的计数指示 到参考时间段的开始。

    TRANSITION DETECTION CIRCUITRY AND METHOD OF DETECTING A TRANSITION OF A SIGNAL OCCURRING WITHIN A TIMING WINDOW
    8.
    发明申请
    TRANSITION DETECTION CIRCUITRY AND METHOD OF DETECTING A TRANSITION OF A SIGNAL OCCURRING WITHIN A TIMING WINDOW 审中-公开

    公开(公告)号：US20180138900A1

    公开(公告)日：2018-05-17

    申请号：US15568174

    申请日：2016-03-03

    Applicant: ARM LIMITED

    Inventor： Shidhartha DAS ,  David Michael BULL

    IPC: H03K5/1534 ,  H03K3/037

    CPC classification number: H03K5/1534 ,  H03K3/037 ,  H03K3/0375

    Abstract: A transition detection circuit (20) and method of operation of such a circuit are provided, the transition detection circuit (20) having pulse generation circuitry (25) to receive an input signal (10) and to generate a pulse signal in response to a transition in the input signal, and pulse detection circuitry (30) to assert an error signal on detection of the pulse signal generated by the pulse generation circuitry. The pulse generation circuitry has pulse control circuitry (35) to control a property of the pulse signal dependent on a timing window indication signal (40). In particular, when the pulse signal is generated at least partly whilst the timing window indication signal is set, the pulse control circuitry (35) controls the property of the pulse signal such that generated pulse signal is detected by the pulse detection circuitry (20). In contrast, when the pulse signal is entirely generated whilst the timing window indication signal (40) is cleared, the pulse control circuitry (35) controls the property of the pulse signal such that the generated pulse signal is undetected by the pulse detection circuitry (20). This gives rise to significant area and energy consumption savings, whilst still allowing reliable detection of timing errors.

    INTEGRATED CIRCUIT WITH ERROR REPAIR AND FAULT TOLERANCE
    10.
    发明申请
    INTEGRATED CIRCUIT WITH ERROR REPAIR AND FAULT TOLERANCE 审中-公开
    具有错误维修和故障保修的集成电路

    公开(公告)号：US20140068371A1

    公开(公告)日：2014-03-06

    申请号：US14079276

    申请日：2013-11-13

    Applicant: ARM Limited

    Inventor： Shidhartha DAS ,  David Michael BULL ,  Emre OZER

    IPC: G06F11/16

    CPC classification number: G06F11/0793 ,  G01R31/31816 ,  G06F11/1076 ,  G06F11/1608

    Abstract: An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways.

    Abstract translation: 集成电路具有错误检测电路和错误修复电路。 误差容限电路响应于控制参数来选择性地禁用错误修复电路。 控制参数取决于电路内执行的处理。 例如，控制参数可以根据执行的程序指令，错误的输出信号值，电路的先前行为或其他方式来生成。

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