公开(公告)号：US11581299B2

公开(公告)日：2023-02-14

申请号：US16817588

申请日：2020-03-12

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Carlton T. Creamer ,  Daniel C. Boire ,  Kanin Chu ,  Hong M. Lu ,  Bernard J. Schmanski

IPC: H01L27/02 ,  H04B1/40 ,  H01L23/66

Abstract: Techniques and architecture are disclosed for a method for making a custom circuit comprising forming a common wafer template, selecting at least two elements of the common wafer template to be chosen elements, and adding at least one metal layer to interconnect the chosen elements to form a circuit. The common wafer template includes a plurality of transistors, a plurality of resistors, a plurality of capacitors, and a plurality of bond pads. Final circuit customization of the common wafer template is accomplished by adding at least one metal layer that forms interconnects to passive and active elements in the template in order to complete the circuit.

公开(公告)号：US20200294987A1

公开(公告)日：2020-09-17

申请号：US16817588

申请日：2020-03-12

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Carlton T. Creamer ,  Daniel C. Boire ,  Kanin Chu ,  Hong M. Lu ,  Bernard J. Schmanski

IPC: H01L27/02 ,  H04B1/40 ,  H03H7/38 ,  H01L23/66

Abstract: Techniques and architecture are disclosed for a method for making a custom circuit comprising forming a common wafer template, selecting at least two elements of the common wafer template to be chosen elements, and adding at least one metal layer to interconnect the chosen elements to form a circuit. The common wafer template includes a plurality of transistors, a plurality of resistors, a plurality of capacitors, and a plurality of bond pads. Final circuit customization of the common wafer template is accomplished by adding at least one metal layer that forms interconnects to passive and active elements in the template in order to complete the circuit.