公开(公告)号：US10529820B2

公开(公告)日：2020-01-07

申请号：US14800387

申请日：2015-07-15

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Kanin Chu ,  Pane Chane Chao ,  Carlton T Creamer

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L29/778 ,  H01L27/12 ,  H01L23/373 ,  H01L21/20 ,  H01L21/683 ,  H01L21/04 ,  H01L29/20

Abstract: A GaN on diamond wafer and method for manufacturing the same is provided. The method comprising: disposing a GaN device or wafer on a substrate, having a nucleation layer disposed between the substrate and a GaN layer; affixing the device to a handling wafer; removing the substrate and substantially all the nucleation layer; and bonding the GaN layer to a diamond substrate.

公开(公告)号：US20200294987A1

公开(公告)日：2020-09-17

申请号：US16817588

申请日：2020-03-12

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Carlton T. Creamer ,  Daniel C. Boire ,  Kanin Chu ,  Hong M. Lu ,  Bernard J. Schmanski

IPC: H01L27/02 ,  H04B1/40 ,  H03H7/38 ,  H01L23/66

Abstract: Techniques and architecture are disclosed for a method for making a custom circuit comprising forming a common wafer template, selecting at least two elements of the common wafer template to be chosen elements, and adding at least one metal layer to interconnect the chosen elements to form a circuit. The common wafer template includes a plurality of transistors, a plurality of resistors, a plurality of capacitors, and a plurality of bond pads. Final circuit customization of the common wafer template is accomplished by adding at least one metal layer that forms interconnects to passive and active elements in the template in order to complete the circuit.

公开(公告)号：US20190043709A1

公开(公告)日：2019-02-07

申请号：US14800387

申请日：2015-07-15

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Kanin Chu ,  Pane Chane Chao ,  Carlton T. Creamer

IPC: H01L21/02 ,  H01L21/768 ,  H01L29/16 ,  H01L29/778

CPC classification number: H01L29/66431 ,  H01L21/0254 ,  H01L21/0475 ,  H01L21/2007 ,  H01L21/2011 ,  H01L21/6835 ,  H01L21/76876 ,  H01L23/3732 ,  H01L27/1266 ,  H01L29/2003 ,  H01L29/778 ,  H01L29/7786 ,  H01L2221/68327

Abstract: A GaN on diamond wafer and method for manufacturing the same is provided. The method comprising: disposing a GaN device or wafer on a substrate, having a nucleation layer disposed between the substrate and a GaN layer; affixing the device to a handling wafer; removing the substrate and substantially all the nucleation layer; and bonding the GaN layer to a diamond substrate.

公开(公告)号：US11581299B2

公开(公告)日：2023-02-14

申请号：US16817588

申请日：2020-03-12

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Carlton T. Creamer ,  Daniel C. Boire ,  Kanin Chu ,  Hong M. Lu ,  Bernard J. Schmanski

IPC: H01L27/02 ,  H04B1/40 ,  H01L23/66

Abstract: Techniques and architecture are disclosed for a method for making a custom circuit comprising forming a common wafer template, selecting at least two elements of the common wafer template to be chosen elements, and adding at least one metal layer to interconnect the chosen elements to form a circuit. The common wafer template includes a plurality of transistors, a plurality of resistors, a plurality of capacitors, and a plurality of bond pads. Final circuit customization of the common wafer template is accomplished by adding at least one metal layer that forms interconnects to passive and active elements in the template in order to complete the circuit.

公开(公告)号：US20130341644A1

公开(公告)日：2013-12-26

申请号：US13879696

申请日：2012-07-18

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Robert Actis ,  Pane-chane Chao ,  Bernard J. Schmanski ,  Anthony A. Immorlica ,  Kanin Chu ,  Robert J. Lender, JR. ,  Dong Xu ,  Sue May Jessup

IPC: H01L23/373

CPC classification number: H01L23/373 ,  H01L23/481 ,  H01L23/66 ,  H01L2223/6622 ,  H01L2223/6627 ,  H01L2224/4847 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1421 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00

Abstract: In summary, a vertical metalized transition in the form of a via goes from the back side of a high thermal conductivity substrate and through any semiconductor layers thereon to a patterned metalized strip, with the substrate having a patterned metalized layer on the back side that is provided with a keep away zone dimensioned to provide impedance matching for RF energy coupled through the substrate to the semiconductor device while at the same time permitting the heat generated by the semiconductor device to flow through the high thermal conductivity substrate, through the back side of the substrate and to a beat sink.

Abstract translation: 总而言之，以通孔形式的垂直金属化转变从高导热性衬底的背面开始并通过其上的任何半导体层到图案化的金属化带，衬底在背面具有图案化的金属化层， 具有保留区，其尺寸设置成为通过衬底耦合到半导体器件的RF能量提供阻抗匹配，同时允许由半导体器件产生的热量流过高导热性衬底，通过该衬底的背面 底物和一个水槽。

公开(公告)号：US20130295757A1

公开(公告)日：2013-11-07

申请号：US13875385

申请日：2013-05-02

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Dong Xu ,  Kanin Chu ,  Pane-chane Chao

IPC: H01L21/28

CPC classification number: H01L21/28008 ,  H01L21/28593 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7783

Abstract: A method for fabricating InP-based high electron-mobility transistors (HEMTs) and GaAs-based metamorphic electron-mobility transistors (MHEMTs) by utilizing asymmetrically recessed Γ-gates and self-aligned ohmic electrodes is disclosed. The fabrication starts with mesa isolation, followed by gate recess and gate metal deposition, in which the gate foot is placed asymmetrically in the recess groove, with the offset towards the source. It is important to use Γ-gates as the shadow mask for ohmic metal deposition, because it allows a source-gate spacing as small as 0.1 micron, greatly reducing the critical source resistance, and it retains a relatively large gate-drain spacing, enabling a decent breakdown voltage when coupled with the asymmetric gate recess. It is also critical to maintain a large stem height of the Γ-gates to assure a sufficient gap between the top of the gates and the ohmic metal after its deposition to reduce the parasitic capacitance. The uniqueness of this technology would best fit the applications that require low voltage and/or low DC power consumption.

Abstract translation: 公开了一种通过利用非对称凹入的伽马栅极和自对准欧姆电极制造基于InP的高电子迁移率晶体管（HEMT）和GaAs基变质电子迁移率晶体管（MHEMT）的方法。 制造从台面隔离开始，随后是栅极凹槽和栅极金属沉积，其中栅极脚不对称地放置在凹槽中，偏移到源极。 重要的是使用伽马门作为欧姆金属沉积的阴影掩模，因为它允许源极间距小至0.1微米，大大降低了临界源极电阻，并且保持了较大的栅极 - 漏极间隔，使得 当与非对称栅极凹槽耦合时，具有相当的击穿电压。 保持伽马门的大的杆高度也是至关重要的，以确保栅极顶部和其沉积后的欧姆金属之间的足够间隙以减小寄生电容。 该技术的独特性将最适合需要低电压和/或低直流功耗的应用。