公开(公告)号：US3692942A

公开(公告)日：1972-09-19

申请号：US3692942D

申请日：1971-06-07

Applicant: BELL TELEPHONE LABOR INC

Inventor： INOSE HIROSHI ,  SAITO TADAO ,  TOKUNAGA TAKEHISA ,  TOMIZAWA KENJI

IPC: H04J3/22 ,  H04J3/06 ,  H04J3/16

CPC classification number: H04J3/0626 ,  H04J3/1629 ,  Y10S370/916

Abstract: A time division multiplex communication system operates to combine the transmissions from the plurality of low speed multiplex paths onto a single high speed path having a transmission rate of C. The incoming information from each low speed path is stored in a buffer memory. A gating circuit selectively applies the stored information from the buffer memory to the high speed path in assigned time slots of said high speed path. A control unit connected to each gating circuit selectively enables one of said gating circuits in each time slot of said outgoing path in accordance with an algorithm which applies said stored information to said outgoing path in a quasi-uniform manner.

Abstract translation: 时分复用通信系统将来自多个低速多路复用路径的传输组合到具有传输速率为C的单个高速路径上。来自每个低速路径的输入信息被存储在缓冲存储器中。 门控电路在所述高速路径的分配时隙中选择性地将存储的信息从缓冲存储器应用到高速路径。 连接到每个选通电路的控制单元根据将所述存储的信息以准均匀方式应用于所述输出路径的算法选择性地使所述输出路径的每个时隙中的所述选通电路中的一个启动。