公开(公告)号：US11302752B2

公开(公告)日：2022-04-12

申请号：US16916138

申请日：2020-06-30

Applicant: BOE Technology Group Co., Ltd.

Inventor： Shuo Huang

IPC: H01L27/32 ,  H01L51/52

Abstract: Provided are a display panel and a display apparatus. The display panel includes: a substrate and a plurality of light filters of different colors disposed on the substrate, the light filter including a plurality of sub-light filters arranged in an array, so that when the display panel is in a screen-off state, light emitted from the light filters of different colors is mixed to form white light.

公开(公告)号：US11862098B2

公开(公告)日：2024-01-02

申请号：US17628779

申请日：2021-04-09

Applicant: BOE Technology Group Co., Ltd.

Inventor： Guangliang Shang ,  Jie Zhang ,  Shuo Huang ,  Libin Liu ,  Shiming Shi ,  Hao Liu ,  Haoliang Zheng ,  Xing Yao

IPC: G09G3/3266 ,  G09G3/36 ,  G11C19/28

CPC classification number: G09G3/3266 ,  G09G3/3677 ,  G11C19/28 ,  G09G2300/0852 ,  G09G2310/0286

Abstract: A shift register, a driving method, a driving control circuit and a display device. The method comprises: at a data refresh stage (T10), applying to an input signal end (IP) an input signal having a pulse level, applying a control clock pulse signal to a control clock signal end, and applying a noise reduction clock pulse signal to a noise reduction clock signal end; at a noise reduction holding phase (T21-1), applying a fixed voltage signal to the input signal end (IP), applying a fixed voltage signal to the control clock signal end, and applying a fixed voltage signal to the noise reduction clock signal end; and at a noise reduction enhancement stage (T22-1), applying a fixed voltage signal to the input signal end (IP), applying a fixed voltage signal to the control clock signal end, and applying a clock pulse signal to the noise reduction clock signal end.

公开(公告)号：US11854508B2

公开(公告)日：2023-12-26

申请号：US17921082

申请日：2021-05-12

Applicant: BOE Technology Group Co., Ltd.

Inventor： Guangliang Shang ,  Tian Dong ,  Shuo Huang ,  Can Zheng

IPC: G09G3/36

CPC classification number: G09G3/3674 ,  G09G2310/0286

Abstract: A driving method and device for a shift register. In a data refreshing phase, loading an input signal having a pulse level to an input signal end, loading a control clock pulse signal to a control clock signal end, loading a noise reduction clock pulse signal to a noise reduction clock signal end, controlling a cascade signal end of the shift register to output a cascade signal having a pulse level, and controlling a drive signal end of the shift register to output a drive signal having a pulse level; in a data holding phase, loading a fixed voltage signal to the input signal end, loading a first set signal to the control clock signal end, loading a second set signal to the noise reduction clock signal end, controlling the cascade signal end to output a fixed voltage signal having a second level.