Pixel circuit and method for driving same, display panel, and display device

    公开(公告)号:US11996035B2

    公开(公告)日:2024-05-28

    申请号:US17639790

    申请日:2021-03-11

    IPC分类号: G09G3/32

    摘要: Provided is a pixel circuit. The pixel circuit includes a reset circuit, a data write circuit, a light-emission control circuit, and a drive circuit; wherein the reset circuit is configured to transmit a reset power signal supplied by the reset power terminal to the first node in response to a reset control signal; the data write circuit is configured to transmit a data signal supplied by the data signal terminal to the first node in response to a gate drive signal; the light-emission control circuit is configured to control conduction/non-conduction between the cathode of the light-emitting element and the second node, and control conduction/non-conduction between the third node and the pull-down power terminal, in response to a light-emission control signal; and the drive circuit is configured to control conduction/non-conduction between the second node and the third node in response to a potential of the first node.

    Pixel circuit and control method therefor, display device

    公开(公告)号:US11605348B2

    公开(公告)日:2023-03-14

    申请号:US17433402

    申请日:2020-09-28

    IPC分类号: G09G3/20 G09G3/3258

    摘要: A pixel circuit includes an input circuit and a time control circuit. The input circuit includes a driving transistor, and the input circuit is configured to write a data signal into a gate of the driving transistor in response to a first gate signal, so that the driving transistor outputs a driving signal for driving an element to be driven to emit light according to a gate voltage and a source voltage thereof. The time control circuit is coupled to the input circuit and the element to be driven, and is configured to control the input circuit to transmit the driving signal to the element to be driven for a first duration, and control the input circuit to transmit the driving signal to the element to be driven for a second duration. The second duration is shorter than the first duration, and includes a plurality of phases spaced apart.

    Light-emitting driving circuit and driving method thereof, and light-emitting apparatus

    公开(公告)号:US11568797B2

    公开(公告)日:2023-01-31

    申请号:US17408967

    申请日:2021-08-23

    IPC分类号: G09G3/32

    摘要: A light-emitting driving circuit includes a driving sub-circuit, a control sub-circuit, a data writing sub-circuit and a compensation sub-circuit. The control sub-circuit is configured to initialize voltages of a first node and a control terminal of the driving sub-circuit in response to a second scan signal. The data writing sub-circuit is configured to write a data signal into a first terminal of the driving sub-circuit in response to a first scan signal. The driving sub-circuit is configured to output, from a second terminal of the driving sub-circuit, the data signal and a compensation signal. The compensation sub-circuit is configured to transmit the data signal and the compensation signal to the first node in response to the first scan signal, and adjust the voltage of the control terminal according to the data signal, the compensation signal, the initialized voltages of the first node and the control terminal.

    Pixel driving structure and display panel

    公开(公告)号:US11538404B2

    公开(公告)日:2022-12-27

    申请号:US17476798

    申请日:2021-09-16

    IPC分类号: G09G3/32

    摘要: The present disclosure provides a pixel driving structure and a display panel. The pixel driving structure includes a pulse width modulation driving circuit, a pulse amplitude modulation driving circuit, and a buffer circuit. The pulse width modulation driving circuit is configured to control a pulse width of a driving current supplied to the light emitting device to be driven according to a pulse width modulation data voltage; the pulse amplitude modulation driving circuit is configured to control an amplitude of the driving current supplied to the light emitting device to be driven according to a pulse amplitude modulation data voltage; and the buffer circuit is electrically coupled between the pulse width modulation driving circuit and the pulse amplitude modulation driving circuit and is configured to adjust a rate at which the pulse width modulation driving circuit applies a pulse width modulation voltage to the pulse amplitude modulation driving circuit.