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1.发明授权Construction of LDPC (Low Density Parity Check) codes using GRS (Generalized Reed-Solomon) code 有权使用GRS（广义里德 - 所罗门）代码构建LDPC（低密度奇偶校验）码公开(公告)号：US07536629B2
公开(公告)日：2009-05-19
申请号：US11190333
申请日：2005-07-27
IPC分类号： H03M12/00
CPC分类号： H03M13/255 , H03M7/30 , H03M13/03 , H03M13/033 , H03M13/1102 , H03M13/15 , H03M13/1515
摘要： Construction of LDPC (Low Density Parity Check) codes using GRS (Generalized Reed-Solomon) code. A novel approach is presented by which a GRS code may be employed to generate a wide variety of types of LDPC codes. Such GRS based LDPC codes may be employed within various types of transceiver devices implemented within communication systems. This approach may be employed to generate GRS based LDPC codes particular designed for various application arenas. As one example, such a GRS based LDPC code may be specifically designed for use in communication systems that operate in accordance with any standards and/or recommended practices of the IEEE P802.3an (10GBASE-T) Task Force.
摘要翻译： 使用GRS（广义里德 - 所罗门）代码构建LDPC（低密度奇偶校验）码。 提出了一种新颖的方法，通过该方法可以采用GRS代码来生成各种各样的LDPC码。 这种基于GRS的LDPC码可以在通信系统内实现的各种类型的收发信机中使用。 可以采用该方法来生成针对各种应用领域特别设计的基于GRS的LDPC码。 作为一个示例，这样的基于GRS的LDPC码可以专门设计用于根据IEEE P802.3an（10GBASE-T）任务组的任何标准和/或推荐做法进行操作的通信系统。
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2.发明授权Short length LDPC (Low Density Parity Check) code and modulation adapted for high speed Ethernet applications 失效适用于高速以太网应用的短长度LDPC（低密度奇偶校验）码和调制公开(公告)号：US07559010B2
公开(公告)日：2009-07-07
申请号：US11190657
申请日：2005-07-27
IPC分类号： H03M13/00
CPC分类号： H04L27/04 , H03M13/118 , H03M13/255 , H04L25/4917 , H04L27/3416
摘要： A short length LDPC (Low Density Parity Check) code and modulation adapted for high speed Ethernet applications. In some instances, the short length LDPC code and modulation may be employed within the recommended practices currently being developed by the IEEE 802.3an (10GBASE-T) Task Force. The IEEE 802.3an (10GBASE-T) Task Force has been commissioned to develop and standardize communications protocol adapted particularly for Ethernet operation over 4 wire twisted pair cables. A new LDPC code, some possible embodiments of constellations and the corresponding mappings, as well as possible embodiments of various parity check matrices, H, of the LDPC code are presented herein to provide for better overall performance than other proposed LDPC codes existent in the art of high speed Ethernet applications. Moreover, this proposed LDPC code may be decoded using a communication device having much less complexity than required to decode other proposed LDPC codes existent in this technology space.
摘要翻译： 适用于高速以太网应用的短长度LDPC（低密度奇偶校验）码和调制。 在一些情况下，可以在IEEE 802.3an（10GBASE-T）任务组正在开发的推荐实践中采用短长度LDPC码和调制。 IEEE 802.3an（10GBASE-T）工作组已委托开发和标准化通信协议，特别适用于通过4线双绞线电缆进行以太网操作。 本文中呈现了新的LDPC码，星座的一些可能的实施例和对应的映射以及LDPC码的各种奇偶校验矩阵H的可能实施例，以提供比本领域中存在的其它提出的LDPC码更好的总体性能 的高速以太网应用。 此外，该提出的LDPC码可以使用比在该技术空间中存在的其它提出的LDPC码要求更低的复杂度的通信设备进行解码。
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3.发明授权LDPC (Low Density Parity Check) coded 128 DSQ (Double Square QAM) constellation modulation and associated labeling 失效LDPC（低密度奇偶校验）编码128 DSQ（双方QAM）星座调制和相关标签公开(公告)号：US07515642B2
公开(公告)日：2009-04-07
申请号：US11211210
申请日：2005-08-25
申请人： Gottfried Ungerboeck , Ba-Zhong Shen , Scott Richard Powell , Kelly Brian Cameron , Hau Thien Tran
发明人： Gottfried Ungerboeck , Ba-Zhong Shen , Scott Richard Powell , Kelly Brian Cameron , Hau Thien Tran
IPC分类号： H04L5/12
CPC分类号： H03M13/255 , H03M13/11 , H04L25/4975 , H04L27/3405 , H04L27/3427
摘要： LDPC (Low Density Parity Check) coded 128 DSQ (Double Square QAM) constellation modulation and its associated labeling. A novel means is introduced by which a constellation may be arranged and mapping in its symbols may be determined to provide for improved performance. One application area in which this may be employed is transmission over twisted pair (typically copper) cabling existent within data centers of various networks. The operation of the IEEE 802.3 Ethernet local area networks currently being used (as well as those currently under development) would benefit greatly by employing the various principles presented herein. When this novel approach of an LDPC coded 128 DSQ constellation modulation combined with TH (Tomlinson-Harashima) preceding is employed within a communication device at a transmitter end of a communication channel (i.e., in a transmitter and/or a transceiver), the overall operation of a communication system may improve significantly when compared to prior techniques.
摘要翻译： LDPC（低密度奇偶校验）编码128 DSQ（双方QAM）星座调制及其相关标签。 引入了一种新颖的装置，通过该装置可以布置星座，并且可以确定其符号中的映射以提供改进的性能。 可以采用这种方式的一个应用领域是在各种网络的数据中心内存在的双绞线（通常为铜缆）布线。 目前正在使用的IEEE 802.3以太网局域网（以及目前正在开发中的那些）的运行将通过采用本文呈现的各种原理而受益匪浅。 当在通信信道（即，在发射机和/或收发机）的发射机端的通信设备内采用与TH（Tomlinson-Harashima）组合的LDPC编码的128个DSQ星座调制的新颖方法时， 与现有技术相比，通信系统的操作可以显着改善。
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4.发明授权Amplifying magnitude metric of received signals during iterative decoding of LDPC (Low Density Parity Check) code and LDPC coded modulation 有权在LDPC（低密度奇偶校验）码和LDPC编码调制的迭代解码期间，放大接收信号的幅度度量公开(公告)号：US07401283B2
公开(公告)日：2008-07-15
申请号：US11190334
申请日：2005-07-27
IPC分类号： H03M13/00
CPC分类号： H03M13/658 , H03M13/1111
摘要： Amplifying magnitude metric of received signals during iterative decoding of LDPC code and LDPC coded modulation. By appropriately selecting a metric coefficient value that is used to calculate the initial conditions when decoding LDPC coded signals, a significant reduction in BER may be achieved at certain SNRs. The appropriate selection of the metric coefficient value may be performed depending on the particular SNR at which a communication system is operating. By adjusting this metric coefficient value according to the given LDPC code, modulation, and noise variance, the overall performance of the decoding may be significantly improved. The convergence speed is slowed down so that the decoder will not go to the wrong codeword, and the moving range of the outputs of the decoder is restricted so that the output will not oscillate too much and will eventually move to the correct codeword.
摘要翻译： 在LDPC码和LDPC编码调制的迭代解码期间放大接收信号的幅度度量。 通过在解码LDPC编码信号时适当地选择用于计算初始条件的度量系数值，可以在某些SNR下实现BER的显着降低。 可以根据通信系统正在操作的特定SNR来执行度量系数值的适当选择。 通过根据给定的LDPC码，调制和噪声方差调整该度量系数值，可以显着提高解码的整体性能。 收敛速度变慢，因此解码器不会进入错误的码字，解码器的输出的移动范围受到限制，使得输出不会振荡太多，最终会移动到正确的码字。
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5.发明授权Decoding error correcting codes transmitted through multiple wire twisted pair cables with uneven noise on the wires 有权解码通过多线双绞线电缆传输的错误纠正码，导线上噪声不均匀公开(公告)号：US07587008B2
公开(公告)日：2009-09-08
申请号：US11172551
申请日：2005-06-30
CPC分类号： H04L1/0045 , H03M13/45 , H04L1/02 , H04L25/14 , H04L2001/0096
摘要： Decoding error correcting codes transmitted through multiple wire twisted pair cables with uneven noise on the wires. A novel approach is presented by which the metrics may be calculated for signals received over multi-wire (or alternatively referred to as multi-channel, and/or multi-path) communication channels to exploit an uneven distribution of noise among those wires for improved performance. In addition, this approach may also be performed in combination with employing an amplification factor to modify the metrics employed when performing ECC (Error Correcting Code) decoding. Moreover, when information is known concerning which 1 or more paths (e.g., wires) has an SNR that is different (e.g., lower in some cases) from the others, an even better adapted means of calculating the metrics associated with each of the paths (e.g., wires) may be employed to provide for improved performance with respect to iterative decoding processing of signals encoded using ECCs.
摘要翻译： 解码通过多线双绞线电缆传输的错误纠正码，导线上噪声不均匀。 提出了一种新颖的方法，通过该方法可以针对通过多线（或者称为多通道和/或多路径）通信信道接收的信号计算度量，以利用这些线之间的不均匀分布的噪声来改善 性能。 此外，还可以结合使用放大因子来修改在执行ECC（纠错码）解码时采用的度量来执行该方法。 此外，当已知关于哪个1个或多个路径（例如，线路）具有不同于其他路径（例如，在某些情况下较低的）的SNR的信息时，更好地适用于计算与每个路径相关联的度量的装置 （例如，导线）可用于提供关于使用ECC编码的信号的迭代解码处理的改进的性能。
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公开(公告)号：US20120237032A1
公开(公告)日：2012-09-20
申请号：US13485749
申请日：2012-05-31
CPC分类号： H04L25/03866
摘要： A two-stage block synchronization and scrambling module includes a synchronization PRNG module, a scramble PRNG module, a summing module, and a storage module. The synchronization PRNG module is clocked once per N+1 bit PCS frame (N arbitrary) to produce a synchronization bit and a pseudo-random starting state for the scramble PRNG. The scramble PRNG module is clocked N times per PCS frame to produce a cipher stream starting with a pseudo-random state from the synchronizationPRNG. The summing module is operably coupled to sum the cipher stream and a PCS frame payload to produce scrambled payload. The storage module is operably coupled to store the scrambled payload with the synchronization bit. Synchronization bits from successive frames are a running bit-serial representation of the synchronization PRNG state and are used by the receiver to synchronize with the transmit scrambler.
摘要翻译： 两级块同步和加扰模块包括同步PRNG模块，加扰PRNG模块，求和模块和存储模块。 每N + 1位PCS帧（N任意）为同步PRNG模块计时一次，以产生用于加扰PRNG的同步位和伪随机起始状态。 加扰PRNG模块按照PCS帧为N次计时，以产生从同步PRNG开始的伪随机状态的密码流。 求和模块可操作地耦合以对加密流和PCS帧有效载荷求和以产生加扰有效载荷。 存储模块可操作地耦合以存储具有同步位的加扰有效载荷。 来自连续帧的同步位是同步PRNG状态的运行位串行表示，并被接收机用于与发送扰频器同步。
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公开(公告)号：US08213611B2
公开(公告)日：2012-07-03
申请号：US11255698
申请日：2005-10-21
CPC分类号： H04L25/03866
摘要： A two-stage block synchronization and scrambling module includes a synchronization PRNG module, a scramble PRNG module, a summing module, and a storage module. The synchronization PRNG module is clocked once per N+1 bit PCS frame (N arbitrary) to produce a synchronization bit and a pseudo-random starting state for the scramble PRNG. The scramble PRNG module is clocked N times per PCS frame to produce a cipher stream starting with a pseudo-random state from the synchronization PRNG. The summing module is operably coupled to sum the cipher stream and a PCS frame payload to produce scrambled payload. The storage module is operably coupled to store the scrambled payload with the synchronization bit. Synchronization bits from successive frames are a running bit-serial representation of the synchronization PRNG state and are used by the receiver to synchronize with the transmit scrambler.
摘要翻译： 两级块同步和加扰模块包括同步PRNG模块，加扰PRNG模块，求和模块和存储模块。 每N + 1位PCS帧（N任意）为同步PRNG模块计时一次，以产生用于加扰PRNG的同步位和伪随机起始状态。 加扰PRNG模块按照PCS帧为N次计时，以产生从同步PRNG开始的伪随机状态的密码流。 求和模块可操作地耦合以对加密流和PCS帧有效载荷求和以产生加扰有效载荷。 存储模块可操作地耦合以存储具有同步位的加扰有效载荷。 来自连续帧的同步位是同步PRNG状态的运行位串行表示，并被接收机用于与发送扰频器同步。
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