摘要:
Construction of LDPC (Low Density Parity Check) codes using GRS (Generalized Reed-Solomon) code. A novel approach is presented by which a GRS code may be employed to generate a wide variety of types of LDPC codes. Such GRS based LDPC codes may be employed within various types of transceiver devices implemented within communication systems. This approach may be employed to generate GRS based LDPC codes particular designed for various application arenas. As one example, such a GRS based LDPC code may be specifically designed for use in communication systems that operate in accordance with any standards and/or recommended practices of the IEEE P802.3an (10GBASE-T) Task Force.
摘要:
A short length LDPC (Low Density Parity Check) code and modulation adapted for high speed Ethernet applications. In some instances, the short length LDPC code and modulation may be employed within the recommended practices currently being developed by the IEEE 802.3an (10GBASE-T) Task Force. The IEEE 802.3an (10GBASE-T) Task Force has been commissioned to develop and standardize communications protocol adapted particularly for Ethernet operation over 4 wire twisted pair cables. A new LDPC code, some possible embodiments of constellations and the corresponding mappings, as well as possible embodiments of various parity check matrices, H, of the LDPC code are presented herein to provide for better overall performance than other proposed LDPC codes existent in the art of high speed Ethernet applications. Moreover, this proposed LDPC code may be decoded using a communication device having much less complexity than required to decode other proposed LDPC codes existent in this technology space.
摘要:
LDPC (Low Density Parity Check) coded 128 DSQ (Double Square QAM) constellation modulation and its associated labeling. A novel means is introduced by which a constellation may be arranged and mapping in its symbols may be determined to provide for improved performance. One application area in which this may be employed is transmission over twisted pair (typically copper) cabling existent within data centers of various networks. The operation of the IEEE 802.3 Ethernet local area networks currently being used (as well as those currently under development) would benefit greatly by employing the various principles presented herein. When this novel approach of an LDPC coded 128 DSQ constellation modulation combined with TH (Tomlinson-Harashima) preceding is employed within a communication device at a transmitter end of a communication channel (i.e., in a transmitter and/or a transceiver), the overall operation of a communication system may improve significantly when compared to prior techniques.
摘要:
Amplifying magnitude metric of received signals during iterative decoding of LDPC code and LDPC coded modulation. By appropriately selecting a metric coefficient value that is used to calculate the initial conditions when decoding LDPC coded signals, a significant reduction in BER may be achieved at certain SNRs. The appropriate selection of the metric coefficient value may be performed depending on the particular SNR at which a communication system is operating. By adjusting this metric coefficient value according to the given LDPC code, modulation, and noise variance, the overall performance of the decoding may be significantly improved. The convergence speed is slowed down so that the decoder will not go to the wrong codeword, and the moving range of the outputs of the decoder is restricted so that the output will not oscillate too much and will eventually move to the correct codeword.
摘要:
Decoding error correcting codes transmitted through multiple wire twisted pair cables with uneven noise on the wires. A novel approach is presented by which the metrics may be calculated for signals received over multi-wire (or alternatively referred to as multi-channel, and/or multi-path) communication channels to exploit an uneven distribution of noise among those wires for improved performance. In addition, this approach may also be performed in combination with employing an amplification factor to modify the metrics employed when performing ECC (Error Correcting Code) decoding. Moreover, when information is known concerning which 1 or more paths (e.g., wires) has an SNR that is different (e.g., lower in some cases) from the others, an even better adapted means of calculating the metrics associated with each of the paths (e.g., wires) may be employed to provide for improved performance with respect to iterative decoding processing of signals encoded using ECCs.
摘要:
A two-stage block synchronization and scrambling module includes a synchronization PRNG module, a scramble PRNG module, a summing module, and a storage module. The synchronization PRNG module is clocked once per N+1 bit PCS frame (N arbitrary) to produce a synchronization bit and a pseudo-random starting state for the scramble PRNG. The scramble PRNG module is clocked N times per PCS frame to produce a cipher stream starting with a pseudo-random state from the synchronizationPRNG. The summing module is operably coupled to sum the cipher stream and a PCS frame payload to produce scrambled payload. The storage module is operably coupled to store the scrambled payload with the synchronization bit. Synchronization bits from successive frames are a running bit-serial representation of the synchronization PRNG state and are used by the receiver to synchronize with the transmit scrambler.
摘要:
A two-stage block synchronization and scrambling module includes a synchronization PRNG module, a scramble PRNG module, a summing module, and a storage module. The synchronization PRNG module is clocked once per N+1 bit PCS frame (N arbitrary) to produce a synchronization bit and a pseudo-random starting state for the scramble PRNG. The scramble PRNG module is clocked N times per PCS frame to produce a cipher stream starting with a pseudo-random state from the synchronization PRNG. The summing module is operably coupled to sum the cipher stream and a PCS frame payload to produce scrambled payload. The storage module is operably coupled to store the scrambled payload with the synchronization bit. Synchronization bits from successive frames are a running bit-serial representation of the synchronization PRNG state and are used by the receiver to synchronize with the transmit scrambler.