公开(公告)号：US20060004986A1

公开(公告)日：2006-01-05

申请号：US10530495

申请日：2003-10-01

申请人： Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  Carlos Alba Pinto ,  Harm Johannes Peters ,  Rafael Peset Llopis

发明人： Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  Carlos Alba Pinto ,  Harm Johannes Peters ,  Rafael Peset Llopis

IPC分类号： G06F15/00 ,  G06F12/00

CPC分类号： G06F9/30003 ,  G06F9/30149 ,  G06F9/3802 ,  G06F9/3853

摘要： A data processing apparatus has an instruction memory system arranged to output an instruction word addressed by an instruction address. An instruction execution unit, processes a plurality of instructions from the instruction word in parallel. A detection unit, detects in which of a plurality of ranges the instruction address lies. The detection unit is coupled to the instruction execution unit and/or the instruction memory system, to control a way in which the instruction execution unit parallelizes processing of the instructions from the instruction word, dependent on a detected range. In an embodiment the instruction execution unit and/or the instruction memory system adjusts a width of the instruction word that determines a number of instructions from the instruction word that is processed in parallel, dependent on the detected range.

公开(公告)号：US20060156004A1

公开(公告)日：2006-07-13

申请号：US10530639

申请日：2003-09-17

申请人： Carlos Alba Pinto ,  Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  Harm Johannes Peters ,  Rafael Peset Llopis

发明人： Carlos Alba Pinto ,  Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  Harm Johannes Peters ,  Rafael Peset Llopis

IPC分类号： H04N17/00

CPC分类号： G06F9/3853 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/3012 ,  G06F9/30141 ,  G06F9/30167 ,  G06F9/3869 ,  G06F9/3885 ,  Y02D10/128 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D50/20

摘要： A data processing apparatus has an instruction memory system arranged to output an instruction word, capable of containing a plurality of instructions, respective instruction words being output in response to respective instruction addresses. An instruction execution unit contains a plurality of functional units, each capable of executing a respective instruction from the instruction word in parallel with execution of other instructions from the instruction word by other ones of the functional units. A power saving circuit is provided to switch a selectable subset of the functional units and/or parts of the instruction memory to a power saving state, while other functional units and parts of the instruction memory continue processing instructions in a normal power consuming state. The power saving circuit selects the functional units and/or parts of the instruction memory dependent on program execution.

摘要翻译： 数据处理装置具有指令存储器系统，其被布置为输出能够包含多个指令的指令字，响应于相应的指令地址输出相应的指令字。 指令执行单元包含多个功能单元，每个功能单元能够执行来自指令字的相应指令，并且与其他功能单元从指令字执行其他指令并行执行。 提供省电电路以将功能单元和/或指令存储器的可选择子集切换到省电状态，而指令存储器的其他功能单元和部分在正常功耗状态下继续处理指令。 省电电路根据程序执行选择指令存储器的功能单元和/或部分。

公开(公告)号：US20060095715A1

公开(公告)日：2006-05-04

申请号：US10540698

申请日：2003-12-03

申请人： Balakrishnan Srinivasan ,  Ramanathan Sethuraman ,  Carlos Alba Pinto ,  Harm Johannes Peters

发明人： Balakrishnan Srinivasan ,  Ramanathan Sethuraman ,  Carlos Alba Pinto ,  Harm Johannes Peters

IPC分类号： G06F15/00

CPC分类号： G06F9/3885 ,  G06F9/3853

摘要： The invention relates to a very long instruction word (VLIW) processor comprising a plurality of functional units (110, 130, 135), each for executing an operation, and a VLIW controller (100) connected to each of said functional units (110, 130, 135) and adapted to controlling said functional units (110, 130, 135). The VLIW processor comprises at least one indication means (140) associated with one of said functional units (135) and adapted to registering and indicating to the VLIW controller (100) whether said one functional unit (135) is idle or operating.

摘要翻译： 本发明涉及一种非常长的指令字（VLIW）处理器，它包括多个用于执行操作的功能单元（110,130,135），和连接到每个所述功能单元（110,130,135）的VLIW控制器（100） 130,135），并适于控制所述功能单元（110,130,135）。 所述VLIW处理器包括与所述功能单元（135）之一相关联的至少一个指示装置（140），并且适于向VLIW控制器（100）注册和指示所述一个功能单元（135）是空闲还是操作。