公开(公告)号：US20180287612A1

公开(公告)日：2018-10-04

申请号：US16001701

申请日：2018-06-06

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： HYUNCHUL HWANG ,  MINSU KIM

IPC分类号： H03K19/00

CPC分类号： H03K19/0016 ,  G06F1/3237 ,  H03K19/0013 ,  Y02D10/128

摘要： A clock gating circuit includes a first precharge unit charging a first node based on a clock signal, a second precharge unit charging a second node based on the clock signal, a first discharge unit discharging the first node based on the clock signal, a second discharge unit discharging the second node based on the clock signal, a first cross-coupled maintain unit maintaining the first node at a charge state according to a voltage level of the second node, a second cross-coupled maintain unit maintaining the second node at a charge state according to a voltage level of the first node, and a control unit controlling the first and second discharge units to discharge the first node or the second node on the basis of a clock enable signal.

公开(公告)号：US20180183440A1

公开(公告)日：2018-06-28

申请号：US15676907

申请日：2017-08-14

申请人： GN Hearing A/S

发明人： Dan Raun JENSEN ,  Per ASBECK ,  Frederic HASBANI

IPC分类号： H03K19/0948 ,  H03K3/2885 ,  H03K19/00 ,  H01L27/092 ,  H01L27/12

CPC分类号： H03K19/0948 ,  G06F1/06 ,  G06F1/10 ,  G06F1/3237 ,  H01L27/092 ,  H01L27/1203 ,  H03K3/2885 ,  H03K19/0016 ,  Y02D10/128

摘要： An integrated circuit includes a first logic circuit region comprising a first regional clock network for supplying a first regional clock signal to digital logic circuit(s); and a clock gating circuit to derive the first regional clock signal from a clock signal and selectively apply and interrupt the first regional clock signal in accordance with a state select signal. The first logic circuit region comprises a first back bias voltage grid connected to respective bodies of PMOS transistors of the digital logic circuit(s) and a second back bias voltage grid connected to respective bodies of NMOS transistors of the digital logic circuit(s). The integrated circuit further comprises a controllable back bias voltage generator configured to adjust a first back bias voltage of the first back bias voltage grid, and to adjust a back bias voltage of the second back bias voltage grid, in accordance with the state select signal.

公开(公告)号：US20180136707A1

公开(公告)日：2018-05-17

申请号：US15868299

申请日：2018-01-11

申请人： MICRON TECHNOLOGY, INC.

发明人： Chang Wan Ha ,  Hang Tian ,  Jong Kang

IPC分类号： G06F1/32 ,  G11C7/10 ,  G11C7/22 ,  G06F1/12 ,  G06F13/16

CPC分类号： G06F1/324 ,  G06F1/12 ,  G06F1/3237 ,  G06F1/3275 ,  G06F13/1673 ,  G11C7/1015 ,  G11C7/222 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/14

摘要： Apparatus facilitating peak power management include a plurality of dies, with each such die comprising an array of memory cells, a controller for performing access operations on the array of memory cells, and a counter configured to be responsive to a clock signal. A particular die of a first subset of dies of the plurality of dies comprises a clock generator for generating the clock signal. Each die of the first subset of dies is configured to be selectively enabled to receive commands in response to a first chip enable signal, and each die of a second subset of dies of the plurality of dies is configured to be selectively enabled to receive commands in response to a second chip enable signal independent of the first chip enable signal, wherein the first subset of dies and the second subset of dies are mutually exclusive.

公开(公告)号：US20180107623A1

公开(公告)日：2018-04-19

申请号：US15794148

申请日：2017-10-26

申请人： Rambus Inc.

发明人： Yuanlong Wang

IPC分类号： G06F13/42 ,  G06F1/32

CPC分类号： G06F13/4243 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/3275 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D50/20

摘要： The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.

公开(公告)号：US20180095768A1

公开(公告)日：2018-04-05

申请号：US15822261

申请日：2017-11-27

申请人： International Business Machines Corporation

发明人： Juergen Haess ,  Cédric Lichtenau ,  Stefan Payer ,  Kerstin C. Schelm

IPC分类号： G06F9/38 ,  G06F1/32

CPC分类号： G06F9/3869 ,  G06F1/3237 ,  G06F1/3287 ,  Y02D10/128 ,  Y02D10/171

摘要： A system and a method of clock-gating for multicycle instructions are provided. For example, the method includes enabling a plurality of logic blocks that include a subset of multicycle (MC) logic blocks and a subset of pipeline logic blocks. The method also includes computing a precise enable computation value after a plurality of cycles of executing an instruction, and disabling one or more of the subset of multicycle (MC) logic blocks based on the precise enable computation value. Also, at least the subset of pipeline logic blocks needed to compute the instruction remains on.

公开(公告)号：US09886414B2

公开(公告)日：2018-02-06

申请号：US14873485

申请日：2015-10-02

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jaegeun Yun ,  Lingling Liao ,  Bub-chul Jeong

IPC分类号： G06F13/42 ,  G06F1/32 ,  G06F1/10 ,  G06F13/40 ,  G06F13/28 ,  G06F13/364

CPC分类号： G06F13/4291 ,  G06F1/10 ,  G06F1/3237 ,  G06F13/28 ,  G06F13/364 ,  G06F13/405 ,  G06F13/4054 ,  G06F2213/0038 ,  Y02B70/12 ,  Y02B70/123 ,  Y02D10/128 ,  Y02D10/151

摘要： A system-on-chip bus system includes a bus configured to connect function blocks of a system-on-chip to each other, and a clock gating unit connected to an interface unit of the bus and configured to basically gate a clock used in the operation of a bus bridge device mounted on the bus according to a state of a transaction detection signal.

公开(公告)号：US20170285718A1

公开(公告)日：2017-10-05

申请号：US15193125

申请日：2016-06-27

申请人： VIA Technologies, Inc.

发明人： Yi-Lin Lai ,  Chen-Te Chen

IPC分类号： G06F1/32 ,  G06F12/02

CPC分类号： G06F1/324 ,  G06F1/3237 ,  G06F1/3296 ,  G06F12/0238 ,  G06F13/14 ,  G06F2212/222 ,  G06F2212/251 ,  Y02D10/128 ,  Y02D50/20

摘要： A memory apparatus and an energy-saving control method thereof are provided. The memory apparatus includes a plurality of non-volatile memory units and a control chip, and the control chip includes a specific circuit group, a memory control unit and an energy-saving control unit. The memory control unit controls an access to the non-volatile memory units. In a normal mode and during a period of accessing the non-volatile memory units by the control chip, if the non-volatile memory units are in a busy state, the energy-saving control unit controls the clock generation unit to stop outputting an internal clock signal to the specific circuit group, so as to reduce power consumption of the control chip.

公开(公告)号：US09720491B2

公开(公告)日：2017-08-01

申请号：US14752841

申请日：2015-06-27

申请人： Intel Corporation

发明人： Dean Mulla ,  Daniel G. Borkowski ,  Krishnakanth V. Sistla ,  Victor Wu ,  Manev Luthra

IPC分类号： G06F3/06 ,  G06F1/32

CPC分类号： G06F1/3296 ,  G06F1/3225 ,  G06F1/3237 ,  G06F1/3275 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/0653 ,  G06F3/0673 ,  Y02D10/128 ,  Y02D10/14 ,  Y02D10/172

摘要： Systems and methods may provide for determining, in a first domain that manages a state of a second domain, that the second domain is in the state and determining, in the first domain, that a periodic action has been scheduled to occur in the second domain while the second domain is in the state. Additionally, the periodic action may be documented as a missed event with respect to the second domain. In one example, documenting the periodic action as a missed event includes incrementing a missed event counter.

公开(公告)号：US09710041B2

公开(公告)日：2017-07-18

申请号：US14812056

申请日：2015-07-29

申请人： Intel Corporation

发明人： Alexander Gendler ,  Larisa Novakovsky ,  Krishnakanth V. Sistla ,  Vivek Garg ,  Dean Mulla ,  Ashish V. Choubal ,  Erik G. Hallnor ,  Kimberly C. Weier

IPC分类号： G06F1/26 ,  G06F1/32 ,  G06F1/04 ,  G06F9/38 ,  G06F15/17

CPC分类号： G06F1/3203 ,  G06F1/04 ,  G06F1/26 ,  G06F1/263 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/329 ,  G06F1/3293 ,  G06F9/38 ,  G06F15/163 ,  G06F15/17 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/24 ,  Y02D50/20

摘要： In one embodiment, a processor includes a core to execute instructions and a core perimeter logic coupled to the core. The core perimeter logic may include a fabric interface logic coupled to the core. In turn, the fabric interface logic may include a first storage to store state information of the core when the core is in a low power state, and enable an inter-die interconnect coupled between the core and an uncore to be maintained in an active state during entry of the core into a low power state. Other embodiments are described and claimed.

公开(公告)号：US09658676B1

公开(公告)日：2017-05-23

申请号：US14626716

申请日：2015-02-19

申请人： Amazon Technologies, Inc.

发明人： Richard Thomas Witek ,  Long Li ,  Maya Suresh

IPC分类号： G06F1/32 ,  G06F13/24 ,  G06F5/14

CPC分类号： G06F1/3237 ,  G06F1/3228 ,  G06F5/14 ,  G06F13/24 ,  G06F15/7825 ,  Y02D10/128

摘要： Subject matter disclosed herein relates to arrangements and techniques for sending messages directly among processing cores and directly among co-processors over a network-on-chip (NoC). More particularly, the present disclosure provides an Application Specific Integrated Circuit (ASIC) that includes processing cores coupled together with a NoC. Each processing core and co-processor includes two corresponding buffers. A first buffer is for sending messages and a second buffer is for receiving messages. Messages are sent from a processing core directly to another processing core through the NoC. Messages are also sent from a co-processor directly to another co-processor through the NoC.