公开(公告)号：US20200254487A1

公开(公告)日：2020-08-13

申请号：US16784186

申请日：2020-02-06

Applicant: Butterfly Network, Inc.

Inventor： Lingyun Miao ,  Jianwei Liu ,  Jonathan M. Rothberg

IPC: B06B1/06 ,  A61B8/12 ,  A61B8/00

Abstract: A method of forming an ultrasonic transducer device includes forming a patterned metal electrode layer over a substrate, the patterned metal electrode layer comprising a lower layer and an upper layer formed on the lower layer; forming an insulation layer over the patterned metal electrode layer; and planarizing the insulation layer to the upper layer of the patterned metal electrode layer, wherein the upper layer comprises a electrically conductive material that serves as a chemical mechanical polishing (CMP) stop layer that has CMP selectivity with respect to the insulation layer and the lower layer, and wherein the upper layer has a CMP removal rate slower than that of the insulation layer.

公开(公告)号：US10856844B2

公开(公告)日：2020-12-08

申请号：US16401249

申请日：2019-05-02

Applicant: Butterfly Network, Inc.

Inventor： Keith G. Fife ,  Jianwei Liu

IPC: H01L29/84 ,  A61B8/00 ,  H01L41/293 ,  H01L41/113

Abstract: Vertical packaging configurations for ultrasound chips are described. Vertical packaging may involve use of integrated interconnects other than wires for wire bonding. Examples of such integrated interconnects include edge-contact vias, through silicon vias and conductive pillars. Edge-contact vias are vias defined in a trench formed in the ultrasound chip. Multiple vias may be provided for each trench, thus increasing the density of vias. Such vias enable electric access to the ultrasound transducers. Through silicon vias are formed through the silicon handle and provide access from the bottom surface of the ultrasound chip. Conductive pillars, including copper pillars, are disposed around the perimeter of an ultrasound chip and provide access to the ultrasound transducers from the top surface of the chip. Use of these types of packaging techniques can enable a substantial reduction in the dimensions of an ultrasound device.

公开(公告)号：US20200269279A1

公开(公告)日：2020-08-27

申请号：US16683750

申请日：2019-11-14

Applicant: Butterfly Network, Inc.

Inventor： Lingyun Miao ,  Jianwei Liu ,  Keith G. Fife

IPC: B06B1/02 ,  B81B3/00 ,  B81C1/00

Abstract: A method of forming an ultrasonic transducer device includes forming and patterning a film stack over a substrate, the film stack comprising a metal electrode layer and a chemical mechanical polishing (CMP) stop layer formed over the metal electrode layer; forming an insulation layer over the patterned film stack; planarizing the insulation layer to the CMP stop layer; measuring a remaining thickness of the CMP stop layer; and forming a membrane support layer over the patterned film stack, wherein the membrane support layer is formed at thickness dependent upon the measured remaining thickness of the CMP stop layer, such that a combined thickness of the CMP stop layer and the membrane support layer corresponds to a desired transducer cavity depth.

公开(公告)号：US20200147641A1

公开(公告)日：2020-05-14

申请号：US16680956

申请日：2019-11-12

Applicant: Butterfly Network, Inc.

Inventor： Keith G. Fife ,  Lingyun Miao ,  Jianwei Liu ,  Jonathan M. Rothberg

IPC: B06B1/02 ,  B81B7/00 ,  B81C1/00 ,  A61B8/00

Abstract: A method of forming an ultrasonic transducer device includes bonding a membrane to seal a transducer cavity with at least a portion of a getter material layer being exposed, the getter material layer comprising a portion of a bilayer stack compatible for use in damascene processing.

公开(公告)号：US20210296195A1

公开(公告)日：2021-09-23

申请号：US17191829

申请日：2021-03-04

Applicant: Butterfly Network, Inc.

Inventor： Jianwei Liu ,  Keith G. Fife

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  A61B8/00

Abstract: Described herein are methods and apparatuses for packaging an ultrasound-on-a-chip. An ultrasound-on-a-chip may be coupled to a redistribution layer and to an interposer layer. Encapsulation may encapsulate the ultrasound-on-a-chip device and first metal pillars may extend through the encapsulation and electrically couple to the redistribution layer. Second metal pillars may extend through the interposer layer. The interposer layer may include aluminum nitride. The first metal pillars may be electrically coupled to the second metal pillars. A printed circuit board may be coupled to the interposer layer.

公开(公告)号：US11018068B2

公开(公告)日：2021-05-25

申请号：US16502553

申请日：2019-07-03

Applicant: Butterfly Network, Inc.

Inventor： Jianwei Liu ,  Keith G. Fife

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  A61B8/00

Abstract: Described herein are methods and apparatuses for packaging an ultrasound-on-a-chip. An ultrasound-on-a-chip may be coupled to a redistribution layer and to an interposer layer. Encapsulation may encapsulate the ultrasound-on-a-chip device and first metal pillars may extend through the encapsulation and electrically couple to the redistribution layer. Second metal pillars may extend through the interposer layer. The interposer layer may include aluminum nitride. The first metal pillars may be electrically coupled to the second metal pillars. A printed circuit board may be coupled to the interposer layer.

公开(公告)号：US20210113188A1

公开(公告)日：2021-04-22

申请号：US17088336

申请日：2020-11-03

Applicant: Butterfly Network, Inc.

Inventor： Keith G. Fife ,  Jianwei Liu

IPC: A61B8/00 ,  H01L41/293 ,  H01L41/113

Abstract: Vertical packaging configurations for ultrasound chips are described. Vertical packaging may involve use of integrated interconnects other than wires for wire bonding. Examples of such integrated interconnects include edge-contact vias, through silicon vias and conductive pillars. Edge-contact vias are vias defined in a trench formed in the ultrasound chip. Multiple vias may be provided for each trench, thus increasing the density of vias. Such vias enable electric access to the ultrasound transducers. Through silicon vias are formed through the silicon handle and provide access from the bottom surface of the ultrasound chip. Conductive pillars, including copper pillars, are disposed around the perimeter of an ultrasound chip and provide access to the ultrasound transducers from the top surface of the chip. Use of these types of packaging techniques can enable a substantial reduction in the dimensions of an ultrasound device.

公开(公告)号：US20210038193A1

公开(公告)日：2021-02-11

申请号：US16988125

申请日：2020-08-07

Applicant: Butterfly Network, Inc.

Inventor： Jianwei Liu ,  Lingyun Miao ,  Sarp Satir

IPC: A61B8/00 ,  B06B1/06 ,  H04R31/00

Abstract: An ultrasonic transducer device is provided. In some embodiments, the ultrasonic transducer device includes a substrate having a membrane support layer formed on a bottom cavity layer, and an opening in the membrane support layer so as to form a transducer cavity. In some embodiments, the opening comprises a truncated circle shape.

公开(公告)号：US20200239299A1

公开(公告)日：2020-07-30

申请号：US16774956

申请日：2020-01-28

Applicant: Butterfly Network, Inc.

Inventor： Jianwei Liu ,  Keith G. Fife

IPC: B81B7/00 ,  B06B1/02 ,  B81C1/00

Abstract: A method of forming a multiple layer, hybrid interposer structure includes forming a plurality of first openings through a substrate, the substrate comprising a heat spreading material; forming a first metal material within the plurality of first openings and on top and bottom surfaces of the substrate; patterning the first metal material; forming a dielectric layer over the patterned first metal material; forming a plurality of second openings within the dielectric layer to expose portions of the patterned first metal material on the top and bottom surfaces of the substrate; filling the plurality of second openings with a second metal material, in contact with the exposed portions of the patterned first metal material; forming a third metal material on the top and bottom surfaces of the substrate, the third metal material in contact with the second metal material and the dielectric layer; and patterning the third metal material.

公开(公告)号：US20210183832A1

公开(公告)日：2021-06-17

申请号：US17124100

申请日：2020-12-16

Applicant: Butterfly Network, Inc.

Inventor： Kailiang Chen ,  Nevada J. Sanchez ,  Jianwei Liu

IPC: H01L25/16 ,  B06B1/02 ,  H01L27/20 ,  H01L41/04 ,  H01L41/047 ,  H01L41/25 ,  H01L41/29

Abstract: Aspects of the technology described herein related to an ultrasound device including a first integrated circuit substrate having first integrated ultrasound circuitry and a second integrated circuit substrate having second integrated ultrasound circuitry. The first and second integrated circuit substrates are arranged in a vertical stack. A first conductive pillar is electrically coupled, through a first redistribution layer, to the first integrated circuit substrate, and a second conductive pillar is electrically coupled, through the first and second redistribution layers, to the second integrated circuit substrate.