Processor socket bridge for input/output extension

    公开(公告)号:US11604755B2

    公开(公告)日:2023-03-14

    申请号:US17196124

    申请日:2021-03-09

    Abstract: Presented herein are improvement to computer system architecture. In one embodiment, a method includes reconfiguring system interconnect links disposed between a first central processing unit socket and a second central processing unit socket, disposed together on a single motherboard, as peripheral bus links; and transmitting electrical signals, via the peripheral bus links, and via a printed circuit board that bridges the second central processing unit socket, to at least one input/output functional block that is disposed on the single motherboard and that is selectively connectable to the second central processing unit socket.

    INTERCONNECT METHOD FOR IMPLEMENTING SCALE-UP SERVERS

    公开(公告)号:US20180019953A1

    公开(公告)日:2018-01-18

    申请号:US15210722

    申请日:2016-07-14

    CPC classification number: H04L67/2842 H04L67/1095

    Abstract: An embodiment includes a first server including a first processor electrically connected to a second processor; a second server including a third processor electrically connected to a fourth processor; a first connection plane, wherein one of the first and second processors is connected to one of the third and fourth processors by a first connection via the first connection plane and one of the first and second processors is connected to one of the third and fourth processors by a second connection via the first connection plane; and a second connection plane, wherein one of the first and second processors is connected to one of the third and fourth processors by a third connection via the second connection plane and wherein one of the first and second processors is connected to one of the third and fourth processors by a fourth connection via the second connection plane.

    PROCESSOR SOCKET BRIDGE FOR INPUT/OUTPUT EXTENSION

    公开(公告)号:US20220292041A1

    公开(公告)日:2022-09-15

    申请号:US17196124

    申请日:2021-03-09

    Abstract: Presented herein are improvement to computer system architecture. In one embodiment, a method includes reconfiguring system interconnect links disposed between a first central processing unit socket and a second central processing unit socket, disposed together on a single motherboard, as peripheral bus links; and transmitting electrical signals, via the peripheral bus links, and via a printed circuit board that bridges the second central processing unit socket, to at least one input/output functional block that is disposed on the single motherboard and that is selectively connectable to the second central processing unit socket.

Patent Agency Ranking