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    Processor socket bridge for input/output extension
    1.
    发明授权
    Processor socket bridge for input/output extension 有权

    公开(公告)号：US11604755B2

    公开(公告)日：2023-03-14

    申请号：US17196124

    申请日：2021-03-09

    Applicant: Cisco Technology, Inc.

    Inventor： Jayaprakash Balachandran ,  Bidyut Kanti Sen ,  Kenny Lieu ,  Dattatri N. Mattur

    IPC: G06F13/40 ,  G06F3/12 ,  H05K7/10

    Abstract: Presented herein are improvement to computer system architecture. In one embodiment, a method includes reconfiguring system interconnect links disposed between a first central processing unit socket and a second central processing unit socket, disposed together on a single motherboard, as peripheral bus links; and transmitting electrical signals, via the peripheral bus links, and via a printed circuit board that bridges the second central processing unit socket, to at least one input/output functional block that is disposed on the single motherboard and that is selectively connectable to the second central processing unit socket.

    AGGREGATION OF MULTIPLEXED OPTICAL TRANSCEIVERS IN SERVER CHASSIS TO ESTABLISH FABRIC TOPOLOGY
    4.
    发明公开
    AGGREGATION OF MULTIPLEXED OPTICAL TRANSCEIVERS IN SERVER CHASSIS TO ESTABLISH FABRIC TOPOLOGY 审中-公开

    公开(公告)号：US20230362519A1

    公开(公告)日：2023-11-09

    申请号：US18098616

    申请日：2023-01-18

    Applicant: Cisco Technology, Inc.

    Inventor： Jayaprakash Balachandran ,  Anant Thakar ,  Bidyut Sen

    IPC: H04Q11/00 ,  H04L49/1515

    CPC classification number: H04Q11/0005 ,  H04L49/1515 ,  H04Q11/0067 ,  H04Q2011/0073 ,  H04Q2011/0016 ,  H04Q2011/0052

    Abstract: This disclosure describes multiplexed optical transceivers, such as DWDM multiplexer/demultiplexers, which are aggregated in a server chassis to establish a fabric topology interconnecting blade servers to a dedicated switch module. Blade servers installed in the server chassis can utilize not just Ethernet interfaces to connect to network segments, but also PCIe interfaces as well as a combination of Ethernet and PCIe interfaces. The aggregated optical transceivers multiplex and demultiplex wavelength-specific optical signals using a laser source, reducing power consumption over switched fabric ASICs. Servicing of the multiplexed optical transceivers is facilitated by installation and replacement of a laser source. Scaling and redundancy of fabric topology interconnects can be facilitated by selection of laser sources generating expanded ranges of discrete wavelengths. Furthermore, chassis management can be facilitated by configuring network controllers of blade servers to transport chassis management instructions over the fabric topology in-band over a network interface, rather than by an out-of-band pathway.

    INTERCONNECT METHOD FOR IMPLEMENTING SCALE-UP SERVERS
    6.
    发明申请
    INTERCONNECT METHOD FOR IMPLEMENTING SCALE-UP SERVERS 审中-公开

    公开(公告)号：US20180019953A1

    公开(公告)日：2018-01-18

    申请号：US15210722

    申请日：2016-07-14

    Applicant: CISCO TECHNOLOGY, INC.

    Inventor： Victor Odisho ,  Bidyut Kanti Sen ,  Jayaprakash Balachandran ,  Michael Leung

    IPC: H04L12/927 ,  H04L29/08

    CPC classification number: H04L67/2842 ,  H04L67/1095

    Abstract: An embodiment includes a first server including a first processor electrically connected to a second processor; a second server including a third processor electrically connected to a fourth processor; a first connection plane, wherein one of the first and second processors is connected to one of the third and fourth processors by a first connection via the first connection plane and one of the first and second processors is connected to one of the third and fourth processors by a second connection via the first connection plane; and a second connection plane, wherein one of the first and second processors is connected to one of the third and fourth processors by a third connection via the second connection plane and wherein one of the first and second processors is connected to one of the third and fourth processors by a fourth connection via the second connection plane.

    PROCESSOR SOCKET BRIDGE FOR INPUT/OUTPUT EXTENSION
    7.
    发明申请
    PROCESSOR SOCKET BRIDGE FOR INPUT/OUTPUT EXTENSION 有权

    公开(公告)号：US20220292041A1

    公开(公告)日：2022-09-15

    申请号：US17196124

    申请日：2021-03-09

    Applicant: Cisco Technology, Inc.

    Inventor： Jayaprakash Balachandran ,  Bidyut Kanti Sen ,  Kenny Lieu ,  Dattatri N. Mattur

    IPC: G06F13/40 ,  H05K7/10

    Abstract: Presented herein are improvement to computer system architecture. In one embodiment, a method includes reconfiguring system interconnect links disposed between a first central processing unit socket and a second central processing unit socket, disposed together on a single motherboard, as peripheral bus links; and transmitting electrical signals, via the peripheral bus links, and via a printed circuit board that bridges the second central processing unit socket, to at least one input/output functional block that is disposed on the single motherboard and that is selectively connectable to the second central processing unit socket.

    MULTI-SOCKET SERVER ASSEMBLY
    8.
    发明申请
    MULTI-SOCKET SERVER ASSEMBLY 审中-公开

    公开(公告)号：US20200288571A1

    公开(公告)日：2020-09-10

    申请号：US16294277

    申请日：2019-03-06

    Applicant: Cisco Technology, Inc.

    Inventor： Anant Thakar ,  Jayaprakash Balachandran ,  Daniel Bernard Hruska

    IPC: H05K1/11 ,  H05K5/02

    Abstract: In some examples, a printed circuit board assembly can include a printed circuit board having four (4) central processor unit (CPU) sockets disposed thereon and sixty four (64) dual in-line memory modules (DIMMs) disposed thereon. The printed circuit board can have a top surface and a bottom surface with two (2) CPU sockets and thirty two (32) DIMMs disposed on the top surface and two (2) CPU sockets and thirty two (32) DIMMs disposed on the bottom surface.

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