公开(公告)号：US11711088B2

公开(公告)日：2023-07-25

申请号：US17419548

申请日：2019-12-23

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Chen Li ,  Hao Wang

IPC: H03M1/00 ,  H03M1/06

CPC classification number: H03M1/002 ,  H03M1/0624

Abstract: An analog-to-digital converter and a clock generation circuit thereof are provided. The clock generation circuit comprises cascaded clock generation modules. The clock generation module at each stage is configured to generate a corresponding internal clock signal, and each stage of the clock generation module comprises a delay module and a logic gate module. The second input end of the N-th stage of the logic gate module is connected to the output end of the previous stage of the logic gate module, and the output end of the logic gate module is configured to output an internal clock, so that each stage of the clock generation module can generate one internal clock signal.