摘要:
An analog front-end (AFE) circuit of a digital display is disclosed including: a first circuit to intermittently invert a working clock to generate a control signal and to generate a sampling signal, wherein the sampling signal is corresponding to the working clock; a first analog-to-digital converter (ADC) coupled to the first circuit for converting an analog video signal into a first digital video signal according to the sampling signal; a second analog-to-digital converter coupled to the first circuit for converting the analog video signal into a second digital video signal according to the sampling signal; and a first multiplexer for selectively outputting the first digital video signal or the second digital video signal according to the control signal.
摘要:
An analog front-end (AFE) circuit of a digital display is disclosed including: a first circuit to intermittently invert a working clock to generate a control signal and to generate a sampling signal, wherein the sampling signal is corresponding to the working clock; a first analog-to-digital converter (ADC) coupled to the first circuit for converting an analog video signal into a first digital video signal according to the sampling signal; a second analog-to-digital converter coupled to the first circuit for converting the analog video signal into a second digital video signal according to the sampling signal; and a first multiplexer for selectively outputting the first digital video signal or the second digital video signal according to the control signal.
摘要:
The invention relates to an image processing chip and related method. The image processing chip includes a pin for receiving a composite signal; a synchronization signal detecting circuit, coupled to the pin, for extracting a synchronization signal from the composite signal; a clamping circuit, coupled to the pin, for adjusting a voltage level of the composite signal according to the synchronization signal; and an analog to digital converter, coupled to the pin, for generating a video signal by sampling the composite signal.
摘要:
The invention relates to an image processing chip and related method. The image processing chip includes a pin for receiving a composite signal; a synchronization signal detecting circuit, coupled to the pin, for extracting a synchronization signal from the composite signal; a clamping circuit, coupled to the pin, for adjusting a voltage level of the composite signal according to the synchronization signal; and an analog to digital converter, coupled to the pin, for generating a video signal by sampling the composite signal.
摘要:
An image signal processing method adapted to an AFE device, which respectively generates first and second colors of digital signals according to first and second colors of analog signals. First, the first color of odd and even signals and the second color of odd and even signals are generated according to the first and second colors of analog signals, respectively. In a single channel mode, the first color of odd or even signal serves as the first color of digital signal for output, and the second color of odd or even signal serves as the second color of digital signal for output. In a dual channel mode, the first color of odd signal and second color of even signal are synchronously outputted, and the first color of even signal and second color of odd signal are also synchronously outputted. The first color of odd and even signals are combined to form the first color of digital signal, and the second color of odd and even signals are combined to form the second color of digital signal.
摘要:
A sync signal acquisition device is disclosed which comprises a transistor, a resistor, a clamper, an analog multiplexer and a comparator. While operating in a composite HS mode, prior to the generation of the sync signal HS, the invention uses a conventional circuit to extract a composite sync signal at start-up, thereby allowing related circuits to generate the sync signal HS and a clamping signal. Then, a mode selecting signal is used to disable the automatic clamping mode and switch the analog multiplexer to a forced clamping mode. At this point, the output voltage of the damper is set by a user instead of process; accordingly, the DC voltage level is more controllable, but not subject to drift due to process changes or temperature changes.
摘要:
The invention discloses an analog front end device comprising a band-gap voltage reference circuit and at least one conversion circuit, wherein the conversion circuit includes a clamper, an input buffer, a low-pass filter, a high frequency gain unit and an analog to digital converter. The analog front end device utilize a high frequency gain unit to increase high frequency gain of the image analog signal for increasing the usable number of sampling phase of the image analog signal.
摘要:
A sync signal acquisition device is disclosed which comprises a transistor, a resistor, a clamper, an analog multiplexer and a comparator. While operating in a composite HS mode, prior to the generation of the sync signal HS, the invention uses a conventional circuit to extract a composite sync signal at start-up, thereby allowing related circuits to generate the sync signal HS and a clamping signal. Then, a mode selecting signal is used to disable the automatic clamping mode and switch the analog multiplexer to a forced clamping mode. At this point, the output voltage of the damper is set by a user instead of process; accordingly, the DC voltage level is more controllable, but not subject to drift due to process changes or temperature changes.
摘要:
An analog front-end (AFE) circuit of a digital display is disclosed including: a first analog-to-digital converter (ADC) for converting a first analog video signal into a first digital video signal according to a first sampling signal; a second ADC for converting the first analog video signal into a second digital video signal according to the first sampling signal; a first multiplexer for selectively outputting the first digital video signal or the second digital video signal according to a first output order; and a first clock control circuit for randomly adjusting the first output order of the first and the second digital video signals.
摘要:
A DC level redistribution method includes the steps of: receiving all positive signals and one negative signal of a plurality of pairs of differential signals; fixing a DC level of a positive signal of a designated pair of differential signals among a plurality of pairs of differential signals as a reference in order to adjust a DC level of a negative signal of the designated pair of differential signals for generating an adjusted negative signal; and taking the adjusted negative signal of the designated pair of differential signals as a reference in order to adjust DC levels of the positive signals of the other pairs of differential signals excluding the designated pair of differential signals. The DC redistribution method may be used in a display system.