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公开(公告)号：US11764799B2
公开(公告)日：2023-09-19
申请号：US17569061
申请日：2022-01-05
申请人： IMEC VZW
发明人： Jan Craninckx , Ewout Martens
CPC分类号： H03M1/1215 , H03M1/1023 , H03M1/187 , H03M1/56 , H04N5/06 , H04N25/75 , H03M1/123
摘要： Example embodiments relate to time-interleaved analog-to-digital converters and conversion methods thereof. One embodiment includes a slope analog-to-digital converter. The slope analog-to-digital converter includes a sample and hold stage configured to sample an analog input signal at a sampling frequency. The slope analog-to-digital converter also includes a comparator downstream to the sample and hold stage configured to compare the analog input signal to a slope signal. Further, the slope analog-to-digital converter includes a digital logic configured to receive a counter value corresponding to a voltage level of the slope signal and to sample the counter value based upon the comparison, thereby generating a digital representation of the analog input signal based upon the comparison. The slope signal is asynchronous to the sampling frequency.
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公开(公告)号：US20190238148A1
公开(公告)日：2019-08-01
申请号：US16378532
申请日：2019-04-08
发明人： Daniel Van Blerkom
CPC分类号： H03M1/1215 , H03M1/1205 , H03M1/122 , H03M1/123 , H03M1/38 , H03M1/40 , H03M1/403 , H03M1/46 , H03M1/462 , H03M1/464 , H03M1/466 , H03M1/468
摘要： Methods and systems for analog-to-digital conversion using two side branches that may be operated with overlapped timing such that a sampling phase may be overlapped with a previous conversion phase. Some embodiments provide a method of successive approximation A/D converting, comprising sampling a first signal onto a first capacitor that is configured to selectively couple to an analog input of a comparator, sampling a second signal onto capacitors that are coupled to a second analog input of the comparator and configured for charge redistribution successive approximation A/D conversion; carrying out, based on the first signal and the second signal, a charge redistribution successive approximation A/D conversion using the capacitors; and while carrying out the charge redistribution successive approximation A/D conversion based on the first and second signals, sampling a third signal onto a third capacitor that is configured to selectively couple to the analog input of a comparator.
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公开(公告)号：US20190214972A1
公开(公告)日：2019-07-11
申请号：US16299299
申请日：2019-03-12
CPC分类号： H03H17/0219 , G06F5/01 , G06F7/5443 , H03H17/0045 , H03H17/06 , H03M1/0626 , H03M1/12 , H03M1/1215
摘要： In accordance with an example, an integrated circuit includes a linear combiner having an input for receiving a signal. The linear combiner also has a plurality of operator circuits for applying weighting factors to the signal, in which a first operator circuit in the plurality of operator circuits performs a first operation on the signal using a first sub-weight of one of the weighting factors to provide a first tile output and a second operator circuit in the plurality of operator circuits performs a second operation on the signal using a second sub-weight of the one of the weighting factors to provide a second tile output. The linear combiner also has an adder having a first input coupled to receive the first tile output and the second tile outputs and providing a combined output.
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公开(公告)号：US20180374520A1
公开(公告)日：2018-12-27
申请号：US16117509
申请日：2018-08-30
摘要： Examples disclosed herein relate to a circuit having first and second analog processors and an analog-to-digital converter coupled to the first and second analog processors. The first analog processor provides a first analog signal having a voltage representing a function of a first vector and a second vector. The second analog processor provides a second analog signal having a voltage representing a function of a binary inverse of the first vector and the second vector. The analog-to-digital converter receives the first analog signal and the second analog signal, compares a signal selected from a group consisting of the first analog signal and the second analog signal to a reference voltage and based on the comparison to the reference voltage, determines a digital result representing the function of the first vector and the second vector.
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5.发明授权公开(公告)号：US10014876B1
公开(公告)日：2018-07-03
申请号：US15451194
申请日：2017-03-06
CPC分类号： H03M1/38 , H03M1/1215 , H03M1/1245
摘要： System and method of buffering sampled signals in a time-interleaved analog-to-digital converter (ADC). When the input voltage to the buffer varies to a different level, a constant reset voltage is supplied to the buffer output that drives a large capacitive load, e.g., composed of an array of sub-ADCs. The reset voltage functions to remove the capacitive effect from a previous output value on the load. As a result, the buffer can buffer the input for the load without introducing intersymbol interference (ISI). A reset switch can be used to control the supply of the reset voltage to the buffer output according to a predetermined clock signal. The reset voltage may be the common mode potential in a differential source follower in the buffer. An additional voltage gain can be advantageously achieved by the buffer with a gain factor being independent of the load capacitance.
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公开(公告)号：US09998138B1
公开(公告)日：2018-06-12
申请号：US15711021
申请日：2017-09-21
发明人： Yan Wang , Chieh-Yu Hsieh , Ji Ma , Seyed Arash Mirhaj , Dinesh Jagannath Alladi
摘要： Multi-channel receiver circuits implemented with time-multiplexed successive approximation register (SAR) analog-to-digital converter (ADC) circuits and methods for operating such receiver circuits are disclosed. One example receiver circuit generally includes a first multiplexer having a plurality of inputs coupled to a plurality of in-phase (I) receive paths associated with different channels of the receiver circuit, a first SAR ADC circuit having an input coupled to an output of the first multiplexer, a second multiplexer having a plurality of inputs coupled to a plurality of quadrature (Q) receive paths associated with the different channels of the receiver circuit, and a second SAR ADC circuit having an input coupled to an output of the second multiplexer.
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公开(公告)号：US09985777B2
公开(公告)日：2018-05-29
申请号：US15419063
申请日：2017-01-30
申请人： MaxLinear, Inc.
发明人： Jianyu Zhu , Sheng-Yu Peng , Rodney Chandler , Pawan Tiwari , Rahul Bhatia , Eric Fogleman
CPC分类号： H04L7/0334 , H03M1/1215 , H03M1/1245
摘要： A radio frequency (RF) receiver may comprise a first sampling module that is operable to sample in a first level at a particular main sampling rate; a plurality of second-level sampling modules, wherein each of the plurality of second-level sampling modules is operable to sample in a second level, an output of the first level, at a second sampling rate that is reduced compared to the main sampling rate; and a plurality of third-level modules, each comprising a plurality of third-stage sampling sub-modules that are operable to sample at a third sampling rate that is reduced compared to the second sampling rate, and a plurality of corresponding analog-to-digital conversion (ADC) sub-modules.
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公开(公告)号：US20180131382A1
公开(公告)日：2018-05-10
申请号：US15865798
申请日：2018-01-09
CPC分类号： H03M1/38 , H03M1/0675 , H03M1/0678 , H03M1/0836 , H03M1/1215 , H03M1/124 , H03M1/14
摘要： Systems and methods for converting analog signals to digital signals. A reference slice is associated with each of a plurality of active slices to balance the loading on an active sampling track and hold amplifier within each active slice. Alternatively, the reference slice is split into a portion having a reference ADC that is shared by a plurality of partial reference slices, each partial reference slice having a partial reference input module.
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9.发明申请公开(公告)号：US20180102784A1
公开(公告)日：2018-04-12
申请号：US15707245
申请日：2017-09-18
申请人： MaxLinear, Inc.
发明人： Raja Pullela , Curtis Ling
摘要： Methods and systems are provided for gain control during communications. A first electronic device may communicated data to a second electronic device; may monitor conditions and/or parameters affecting estimated reception performance at the second electronic device; and may communicated to the second electronic device, via a connection separate from and different than a connection used in communicating the data, information relating to the monitored conditions, to enable adjusting functions relating to reception of the data at the second electronic device. Based on the received information, at least one reception related function in the second electronic device may be controlled. The controlling may include determining, based on the received information, adjustments to the at least one reception related function or to a related parameter. The at least one reception related function may include applying gain to at least a portion of signals received by the second electronic device.
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公开(公告)号：US20180083649A1
公开(公告)日：2018-03-22
申请号：US15675091
申请日：2017-08-11
发明人： Martin Pernull , Peter Bogner
IPC分类号： H03M3/00
CPC分类号： H03M3/368 , G11C27/024 , H03M1/0626 , H03M1/1215 , H03M3/422 , H03M3/496
摘要： A circuit (100) comprises an input terminal (141) which is configured to receive an analog input signal (142). The circuit (100) also comprises a combination element (601) which is configured to combine a number of time-displaced signal values of the input signal (142) to form an analog combination signal (144). The circuit (100) also comprises a quantizer (131) having a converter core which is configured to receive the combination signal (144) via passive charge redistribution from the combination element (601) and to convert it into a digital output signal (145). Such techniques can thus provide for an analog/digital conversion with filtering in the analog domain.
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