公开(公告)号：US06518153B1

公开(公告)日：2003-02-11

申请号：US09562911

申请日：2000-05-02

Applicant: Chi-hui Lin ,  Chung Lin Huang

Inventor： Chi-hui Lin ,  Chung Lin Huang

IPC: H01L913205

CPC classification number: H01L29/66545 ,  H01L21/28061 ,  H01L27/10873 ,  H01L29/4941

Abstract: A method of making embedded DRAM devices having integrated therein a gate electrode of low sheet resistance satisfying the requirement of high performance logic circuitry is provided. The gate electrode on a semiconductor substrate comprises a gate oxide film, a polysilicon film, a metal, a lightly doped diffusion layer, silicon dioxide spacers, and a source/drain diffusion layer. The metal is planted in an opening, where a capped silicon nitride used to occupy, on top the polysilicon film.

Abstract translation: 提供一种制造嵌入式DRAM器件的方法，其中集成了满足高性能逻辑电路要求的低片电阻的栅电极。 半导体衬底上的栅电极包括栅极氧化膜，多晶硅膜，金属，轻掺杂扩散层，二氧化硅间隔物和源极/漏极扩散层。 将金属种植在开口中，其中用于在多晶硅膜顶部占据的封盖氮化硅。