公开(公告)号：US06518153B1

公开(公告)日：2003-02-11

申请号：US09562911

申请日：2000-05-02

Applicant: Chi-hui Lin ,  Chung Lin Huang

Inventor： Chi-hui Lin ,  Chung Lin Huang

IPC: H01L913205

CPC classification number: H01L29/66545 ,  H01L21/28061 ,  H01L27/10873 ,  H01L29/4941

Abstract: A method of making embedded DRAM devices having integrated therein a gate electrode of low sheet resistance satisfying the requirement of high performance logic circuitry is provided. The gate electrode on a semiconductor substrate comprises a gate oxide film, a polysilicon film, a metal, a lightly doped diffusion layer, silicon dioxide spacers, and a source/drain diffusion layer. The metal is planted in an opening, where a capped silicon nitride used to occupy, on top the polysilicon film.

Abstract translation: 提供一种制造嵌入式DRAM器件的方法，其中集成了满足高性能逻辑电路要求的低片电阻的栅电极。 半导体衬底上的栅电极包括栅极氧化膜，多晶硅膜，金属，轻掺杂扩散层，二氧化硅间隔物和源极/漏极扩散层。 将金属种植在开口中，其中用于在多晶硅膜顶部占据的封盖氮化硅。

公开(公告)号：US6100117A

公开(公告)日：2000-08-08

申请号：US62639

申请日：1998-04-20

Applicant: Chung Peng Hao ,  Chung Lin Huang ,  Lee Chung Yuan ,  Pei-Ing Lee ,  Wu Hsiung Chen

Inventor： Chung Peng Hao ,  Chung Lin Huang ,  Lee Chung Yuan ,  Pei-Ing Lee ,  Wu Hsiung Chen

IPC: H01L21/8242 ,  H01L23/525 ,  H01L27/108 ,  H01L21/82

CPC classification number: H01L27/10894 ,  H01L23/5258 ,  H01L27/10897 ,  H01L2924/0002

Abstract: A method for manufacturing DRAM having a redundancy circuit region. The method utilizes a laser beam permeable layer such as a silicon nitride layer to serve as a stop layer in the etching step of the passivation oxide layer. The method removes the conductive layer, serving as the upper electrode of the capacitor, in the redundancy circuit region II. The fuse of the redundancy circuit region II can thereby be easily blown by the laser beam.

Abstract translation: 一种用于制造具有冗余电路区域的DRAM的方法。 该方法在钝化氧化物层的蚀刻步骤中利用诸如氮化硅层的激光束可透过层作为停止层。 该方法在冗余电路区域II中去除用作电容器的上电极的导电层。 因此，冗余电路区域II的熔断体可以容易地被激光束吹制。