公开(公告)号：US08557673B1

公开(公告)日：2013-10-15

申请号：US13476251

申请日：2012-05-21

Applicant: Shin-Bin Huang ,  Cheng-Yeh Hsu ,  Chung-Lin Huang

Inventor： Shin-Bin Huang ,  Cheng-Yeh Hsu ,  Chung-Lin Huang

IPC: H01L21/02

CPC classification number: H01L28/91

Abstract: A manufacturing method of a capacitor structure is provided, which includes the steps of: on a substrate having a first oxide layer, (a) forming a first suspension layer on the first oxide layer; (b) forming a first shallow trench into the first oxide layer above the substrate; (c) forming a second oxide layer filling the first shallow trench; (d) forming a second suspension layer on the second oxide layer; (e) forming a second shallow trench through the second suspension layer into the second oxide layer above the first suspension layer; (f) forming at least one deep trench on the bottom surface of the second shallow trench through the second and the first oxide layers, (g) forming an electrode layer on the inner surface of the deep trench; and (h) removing the first and second oxide layers through the trench openings in the first and the second suspension layers.

Abstract translation: 提供一种电容器结构的制造方法，其包括以下步骤：在具有第一氧化物层的衬底上，（a）在第一氧化物层上形成第一悬浮层; （b）在衬底上方的第一氧化物层中形成第一浅沟槽; （c）形成填充所述第一浅沟槽的第二氧化物层; （d）在第二氧化物层上形成第二悬浮层; （e）通过所述第二悬浮层形成穿过所述第一悬浮层上方的所述第二氧化物层的第二浅沟槽; （f）通过第二和第一氧化物层在第二浅沟槽的底表面上形成至少一个深沟槽，（g）在深沟槽的内表面上形成电极层; 和（h）通过第一和第二悬浮层中的沟槽开口去除第一和第二氧化物层。

公开(公告)号：US20130146954A1

公开(公告)日：2013-06-13

申请号：US13429448

申请日：2012-03-26

Applicant: Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

Inventor： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

IPC: H01L27/088 ,  H01L21/336

CPC classification number: H01L27/0207 ,  H01L27/10876 ,  H01L27/10885

Abstract: The present invention provides a memory array including a substrate, an isolation region, a plurality of active regions, a plurality of buried bit lines, a plurality of word lines, a plurality of drain regions and a plurality of capacitors. The isolation region and the active regions are disposed in the substrate and the active regions are encompassed and isolated by the isolation region. The buried bit lines are disposed in the substrate and extend in the second direction. The word lines are disposed in the substrate extend in the first direction. The drain regions are disposed in the active region not covered by the word lines. The capacitors are disposed on the substrate and electrically connected to the drain regions.

Abstract translation: 本发明提供了一种存储器阵列，其包括衬底，隔离区，多个有源区，多个掩埋位线，多个字线，多个漏极区和多个电容。 隔离区域和有源区域设置在衬底中，并且有源区域被隔离区域包围和隔离。 掩埋位线设置在基板中并沿第二方向延伸。 字线设置在基板中沿第一方向延伸。 漏极区域设置在未被字线覆盖的有源区域中。 电容器设置在基板上并电连接到漏极区域。

公开(公告)号：US20130059442A1

公开(公告)日：2013-03-07

申请号：US13282593

申请日：2011-10-27

Applicant: TZUNG-HAN LEE ,  CHUNG-LIN HUANG

Inventor： TZUNG-HAN LEE ,  CHUNG-LIN HUANG

IPC: H01L21/302

CPC classification number: H01L21/3065 ,  H01L21/3081 ,  H01L21/3083

Abstract: A method for adjusting the trench depth of a substrate has the steps as follows. Forming a patterned covering layer on the substrate, wherein the patterned covering layer defines a wider spacing and a narrower spacing. Forming a wider buffering layer arranged in the wider spacing and a narrower buffering layer arranged in the narrower spacing. The thickness of the narrower buffering layer is thinner than the wider buffering layer. Implementing dry etching process to make the substrate corresponding to the wider and the narrower buffering layers form a plurality of trenches. When etching the wider and the narrower buffering layers, the narrower buffering layer is removed firstly, so that the substrate corresponding to the narrower buffering layer will be etched early than the substrate corresponding to the wider buffering layer.

Abstract translation: 用于调整衬底的沟槽深度的方法具有以下步骤。 在衬底上形成图案化的覆盖层，其中图案化覆盖层限定更宽的间隔和更窄的间隔。 形成更宽的间隔布置的较宽的缓冲层和以较窄的间隔布置的较窄的缓冲层。 较窄的缓冲层的厚度比较宽的缓冲层薄。 实施干蚀刻工艺以使与较宽和较窄缓冲层相对应的衬底形成多个沟槽。 当蚀刻较宽和较窄的缓冲层时，首先去除较窄的缓冲层，使得对应于较窄缓冲层的衬底将比对应于较宽缓冲层的衬底早蚀刻。

公开(公告)号：US20110260230A1

公开(公告)日：2011-10-27

申请号：US12829674

申请日：2010-07-02

Applicant: TZUNG HAN LEE ,  CHUNG-LIN HUANG ,  HSIEN-WEN LIU

Inventor： TZUNG HAN LEE ,  CHUNG-LIN HUANG ,  HSIEN-WEN LIU

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/10891 ,  H01L21/26586 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

Abstract: A memory cell with surrounding word line structures includes an active area; a plurality of first trenches formed on the active area in a first direction, each first trench has a bit line on a sidewall therein; a plurality of second trenches formed on the active area in a second direction, each second trench has two word lines formed correspondingly on the sidewalls in the second trench; and a plurality of transistors formed on the active area. The word line pairs are arranged into a surrounding word line structure. The transistor is controlled by the bit line and the two word lines, thus improving the speed of the transistor.

Abstract translation: 具有周围字线结构的存储单元包括有源区; 在第一方向上形成在有源区上的多个第一沟槽，每个第一沟槽在其侧壁上具有位线; 在第二方向上形成在有源区上的多个第二沟槽，每个第二沟槽具有相应地形成在第二沟槽中的侧壁上的两条字线; 以及形成在有源区上的多个晶体管。 字线对被排列成周围的字线结构。 晶体管由位线和两个字线控制，从而提高晶体管的速度。

公开(公告)号：US07960241B2

公开(公告)日：2011-06-14

申请号：US12698322

申请日：2010-02-02

Applicant: Shin-Bin Huang ,  Tzung-Han Lee ,  Chung-Lin Huang

Inventor： Shin-Bin Huang ,  Tzung-Han Lee ,  Chung-Lin Huang

IPC: H01L21/20

CPC classification number: H01L27/10852 ,  H01L28/90

Abstract: A manufacturing method for double-side capacitor of stack DRAM has steps of: forming a sacrificial structure in the isolating trench and the capacitor trenches; forming a first covering layer and a second covering layer on the sacrificial structure; modifying a part of the second covering layer; removing the un-modified second covering layer and the first covering layer to expose the sacrificial structure; removing the exposed part of the sacrificial structure to expose the electrode layer; removing the exposed electrode layer to expose the oxide layer; and removing the oxide layer and sacrificial structure to form the double-side capacitors.

Abstract translation: 堆叠DRAM的双面电容器的制造方法具有以下步骤：在隔离沟槽和电容器沟槽中形成牺牲结构; 在所述牺牲结构上形成第一覆盖层和第二覆盖层; 修改第二覆盖层的一部分; 去除未改性的第二覆盖层和第一覆盖层以暴露牺牲结构; 去除所述牺牲结构的暴露部分以暴露所述电极层; 去除暴露的电极层以暴露氧化物层; 并去除氧化物层和牺牲结构以形成双面电容器。

公开(公告)号：US20110053337A1

公开(公告)日：2011-03-03

申请号：US12827082

申请日：2010-06-30

Applicant: CHIEN-HSUN CHEN ,  TZUNG HAN LEE ,  CHUNG-LIN HUANG

Inventor： CHIEN-HSUN CHEN ,  TZUNG HAN LEE ,  CHUNG-LIN HUANG

IPC: H01L21/762

CPC classification number: H01L27/10876 ,  H01L21/76224 ,  H01L27/10894

Abstract: A self-alignment method for a recess channel dynamic random access memory includes providing a substrate with a target layer, a barrier layer and a lining layer, wherein the target layer has shallow trench isolation structures; patternizing the lining layer, barrier layer and target layer to form recess trench channels; depositing a dielectric layer onto the recess trench channel; forming an ion doped region in the target layer; removing a portion of the dielectric layer to expose a portion of the recess trench channel; forming a filler layer covered onto the recess trench channel; removing a portion of the filler layer to expose a portion of the recess trench channel; forming a passivation layer onto the recess trench channel; removing the passivation layer on the lining layer; and removing the lining layer to form a plurality of structural monomers disposed at the recess trench channel and protruded from the target layer.

Abstract translation: 用于凹槽通道动态随机存取存储器的自对准方法包括：提供具有目标层，阻挡层和衬里层的衬底，其中所述目标层具有浅沟槽隔离结构; 图案化衬里层，阻挡层和目标层以形成凹槽沟道; 将介电层沉积到凹槽沟道上; 在靶层中形成离子掺杂区; 去除所述电介质层的一部分以暴露所述凹槽沟槽沟道的一部分; 形成覆盖在所述凹槽沟道上的填充层; 去除所述填充层的一部分以暴露所述凹槽沟道的一部分; 在所述凹槽沟道上形成钝化层; 去除衬里层上的钝化层; 并且移除所述衬里层以形成设置在所述凹槽沟道处并从所述目标层突出的多个结构单体。

公开(公告)号：US07868377B2

公开(公告)日：2011-01-11

申请号：US11927616

申请日：2007-10-29

Applicant: Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L29/94

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A flash memory is provided. The flash memory features of having the select gate transistors to include two different channel structures, which are a recessed channel structure and a horizontal channel. Because of the design of the recessed channel structure, the space between the gate conductor lines, which are for interconnecting the select gates of the select gate transistors arranged on the same column, can be shortened. Therefore, the integration of the flash memory can be increased; and the process window of the STI process can be increased as well. In addition, at least one depletion-mode select gate transistor is at one side of the memory cell string. The select gate transistor of the depletion-mode is always turned on.

Abstract translation: 提供闪存。 具有选择栅极晶体管的闪存特征包括两个不同的沟道结构，它们是凹陷沟道结构和水平沟道。 由于凹陷沟道结构的设计，可以缩短用于互连布置在同一列上的选择栅晶体管的选通栅极的栅极导体线之间的空间。 因此，可以增加闪存的集成; 并且可以增加STI过程的处理窗口。 此外，至少一个耗尽型选择栅极晶体管位于存储单元串的一侧。 耗尽模式的选择栅晶体管总是导通。

公开(公告)号：US07682902B2

公开(公告)日：2010-03-23

申请号：US11949786

申请日：2007-12-04

Applicant: Ching-Nan Hsiao ,  Pei-Ing Lee ,  Ming-Cheng Chang ,  Chung-Lin Huang ,  Hsi-Hua Chang ,  Chih-Hsiang Wu

Inventor： Ching-Nan Hsiao ,  Pei-Ing Lee ,  Ming-Cheng Chang ,  Chung-Lin Huang ,  Hsi-Hua Chang ,  Chih-Hsiang Wu

IPC: H01L21/336

CPC classification number: H01L27/11534 ,  H01L21/84 ,  H01L27/11526 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7887

Abstract: A memory structure disclosed in the present invention features a control gate and floating gates being positioned in recessed trenches. A method of fabricating the memory structure includes the steps of first providing a substrate having a first recessed trench. Then, a first gate dielectric layer is formed on the first recessed trench. A first conductive layer is formed on the first gate dielectric layer. After that, the first conductive layer is etched to form a spacer which functions as a floating gate on a sidewall of the first recessed trench. A second recessed trench is formed in a bottom of the first recessed trench. An inter-gate dielectric layer is formed on a surface of the spacer, a sidewall and a bottom of the second recessed trench. A second conductive layer formed to fill up the first and the second recessed trench.

Abstract translation: 本发明公开的存储器结构的特征在于控制栅极和位于凹槽中的浮栅。 一种制造存储器结构的方法包括以下步骤：首先提供具有第一凹槽的衬底。 然后，在第一凹槽上形成第一栅极电介质层。 第一导电层形成在第一栅极介电层上。 之后，蚀刻第一导电层以形成用作第一凹槽的侧壁上的浮动栅极的间隔物。 在第一凹槽的底部形成第二凹槽。 在间隔物的表面，第二凹槽的侧壁和底部上形成栅极间电介质层。 形成为填充第一和第二凹槽的第二导电层。

公开(公告)号：US20090124059A1

公开(公告)日：2009-05-14

申请号：US12035529

申请日：2008-02-22

Applicant: Hung-Ming TSAI ,  Ching-Nan HSIAO ,  Chung-Lin HUANG

Inventor： Hung-Ming TSAI ,  Ching-Nan HSIAO ,  Chung-Lin HUANG

IPC: H01L21/76

CPC classification number: H01L21/823437 ,  H01L21/28273 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/11521

Abstract: A method for forming a semiconductor device, includes the steps of providing a substrate; forming a patterned stack on the substrate including a first dielectric layer on the substrate, a first conductive layer on the first dielectric layer and a mask layer on the first conductive layer, wherein a width of the mask layer is smaller than a width of the first conductive layer; forming a second dielectric layer on the sidewall of the patterned stack; forming a third dielectric layer on the substrate; forming a second conductive layer over the substrate; and removing the mask layer and a portion of the first conductive layer covered by the mask layer to form an opening so as to partially expose the first conductive layer.

Abstract translation: 一种形成半导体器件的方法，包括以下步骤：提供衬底; 在所述衬底上形成图案化的叠层，所述衬底上包括在所述衬底上的第一电介质层，所述第一电介质层上的第一导电层和所述第一导电层上的掩模层，其中所述掩模层的宽度小于所述第一导电层的宽度 导电层; 在所述图案化叠层的侧壁上形成第二电介质层; 在所述基板上形成第三电介质层; 在所述衬底上形成第二导电层; 以及去除所述掩模层和由所述掩模层覆盖的所述第一导电层的一部分以形成开口以部分地暴露所述第一导电层。

公开(公告)号：US06921694B2

公开(公告)日：2005-07-26

申请号：US10442308

申请日：2003-05-19

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L21/28 ,  H01L29/423 ,  H01L21/336

CPC classification number: H01L29/42324 ,  H01L21/28273

Abstract: A method for fabricating a floating gate with multiple tips. A semiconductor substrate is provided, on which an insulating layer and a patterned hard mask layer are sequentially formed. The patterned hard mask layer has an opening to expose the surface of the semiconductor substrate. A conducting layer is conformally formed on the patterned hard mask layer, and the opening is filled with the conducting layer. The conducting layer is planarized to expose the surface of the patterned hard mask layer. The conducting layer is thermally oxidized to form an oxide layer, and the patterned hard mask layer is removed.

Abstract translation: 一种用于制造具有多个尖端的浮动栅极的方法。 提供半导体衬底，其上依次形成绝缘层和图案化的硬掩模层。 图案化的硬掩模层具有露出半导体衬底的表面的开口。 在图案化的硬掩模层上共形形成导电层，并且该开口填充有导电层。 导电层被平坦化以暴露图案化的硬掩模层的表面。 导电层被热氧化以形成氧化物层，去除图案化的硬掩模层。