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1.发明授权Parallel method and apparatus for detecting and completing floating point operations involving special operands 失效用于检测和完成涉及特殊操作数的浮点运算的并行方法和装置
公开(公告)号：US5339266A
公开(公告)日：1994-08-16
申请号：US158324
申请日：1993-11-29
CPC分类号： G06F7/483 , G06F7/49905
摘要： A method and apparatus for detecting and completing floating point operations involving special floating point operands is performed in parallel, via a circuit (24), to the operation of at least one floating point mathematical unit (18, 20or 22). The floating point control (30) along with registers (14 and 16) provide floating point operands and floating point control to the mathematical units (18, 20, and 22). If the mathematical units (18, 20, and 22) cannot perform a proper floating point calculation because of the presence of a special operand, then the circuit (24) will detect the special operand and complete the floating point operation in a proper manner by communicating with the floating point control unit (30).
摘要翻译： 用于检测和完成涉及特殊浮点操作数的浮点运算的方法和装置通过电路（24）并行地执行至少一个浮点数学单元（18,20或22）的操作。 浮点控制（30）以及寄存器（14和16）为数学单元（18,20和22）提供浮点运算和浮点控制。 如果数学单元（18,20和22）由于存在特殊操作数而不能执行适当的浮点计算，则电路（24）将检测特殊操作数，并以适当方式完成浮点运算 与浮点控制单元（30）通信。
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公开(公告)号：US5265258A
公开(公告)日：1993-11-23
申请号：US671236
申请日：1991-03-19
申请人： Eric V. Fiene , Gary A. Mussemann
发明人： Eric V. Fiene , Gary A. Mussemann
CPC分类号： G06F7/74 , G06F9/30043
摘要： In an integrated circuit microprocessor, an M-bit priority encoder circuit indicates the highest priority bit position that is set in a first portion of an N-bit (N generally being greater than M) data word and provides control information regarding the number of bits that are set. If more than one bit is set, the highest priority bit is reset, the first portion is re-analyzed, and highest priority bit information and control information are again provided. If only one bit or no bit is set in the first portion, a second portion is analyzed, and highest priority bit information and control information regarding the second portion is provided. Analysis of the second portion, and of any subsequent portions, continues in similar fashion until no further bit positions are determined to be set in the data word.
摘要翻译： 在集成电路微处理器中，M位优先级编码器电路指示在N位（N一般大于M）数据字的第一部分中设置的最高优先级位位置，并提供关于位数的控制信息 设置。 如果设置了多个位，则优先级最高的位被复位，第一部分被重新分析，并且再次提供最高优先级位信息和控制信息。 如果在第一部分仅设置一位或无位，则分析第二部分，并且提供关于第二部分的最高优先级位信息和控制信息。 第二部分和任何后续部分的分析以类似的方式继续，直到确定未在数据字中设置另外的位位置为止。
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公开(公告)号：US09323691B2
公开(公告)日：2016-04-26
申请号：US13415196
申请日：2012-03-08
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/652
摘要： A memory management unit can receive an address associated with a page size that is unknown to the MMU. The MMU can concurrently determine whether a translation lookaside buffer data array stores a physical address associated with the address based on different portions of the address, where each of the different portions is associated with a different possible page size. This provides for efficient translation lookaside buffer data array access when different programs, employing different page sizes, are concurrently executed at a data processing device.
摘要翻译： 存储器管理单元可以接收与MMU未知的页面大小相关联的地址。 MMU可以同时确定翻译后备缓冲器数据阵列是否基于地址的不同部分存储与地址相关联的物理地址，其中每个不同部分与不同的可能的页面大小相关联。 当在数据处理装置中同时执行使用不同页面大小的不同程序时，这提供了有效的翻译后备缓冲器数据阵列访问。
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公开(公告)号：US20130238875A1
公开(公告)日：2013-09-12
申请号：US13415196
申请日：2012-03-08
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/652
摘要： A memory management unit can receive an address associated with a page size that is unknown to the MMU. The MMU can concurrently determine whether a translation lookaside buffer data array stores a physical address associated with the address based on different portions of the address, where each of the different portions is associated with a different possible page size. This provides for efficient translation lookaside buffer data array access when different programs, employing different page sizes, are concurrently executed at a data processing device.
摘要翻译： 存储器管理单元可以接收与MMU未知的页面大小相关联的地址。 MMU可以同时确定翻译后备缓冲器数据阵列是否基于地址的不同部分存储与地址相关联的物理地址，其中每个不同部分与不同的可能的页面大小相关联。 当在数据处理装置中同时执行使用不同页面大小的不同程序时，这提供了有效的翻译后备缓冲器数据阵列访问。
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5.发明授权Data processing system having translation lookaside buffer valid bits with lock and method therefor 有权具有翻译后备缓冲器有效位的数据处理系统及其锁定方法公开(公告)号：US07185170B2
公开(公告)日：2007-02-27
申请号：US10928399
申请日：2004-08-27
CPC分类号： G06F12/126 , G06F12/1027
摘要： A system (10) translates memory addresses. Processing circuitry (12) provides an effective address to a storage array (14, 16) having a plurality of stored effective addresses, each of the plurality of stored effective addresses having a corresponding pair of a lock bit and a valid bit. An output tag value and a single valid bit are provided to a comparator (18). The lock bit defines one of two predetermined classes of tasks executed by the system. The single valid bit is applicable to both of the two predetermined classes of tasks. The lock bit qualifies the clearing of the single valid bit. The comparator respectively compares the output tag value and the single valid bit with a predetermined effective address and a predetermined bit value. An output hit signal is provided when a match occurs to validate a physical address provided by a physical address array (20).
摘要翻译： 系统（10）翻译存储器地址。 处理电路（12）向具有多个存储的有效地址的存储阵列（14,16）提供有效地址，所述多个存储的有效地址中的每一个具有相应的一对锁定位和有效位。 将输出标签值和单个有效位提供给比较器（18）。 锁定位定义系统执行的两个预定任务类别之一。 单个有效位适用于两个预定类别的任务。 锁定位限定单个有效位的清除。 比较器分别将输出标签值和单个有效位与预定的有效地址和预定位值进行比较。 当发生匹配以验证由物理地址阵列（20）提供的物理地址时，提供输出命中信号。
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