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    Metal stress memorization technology
    1.
    发明授权
    Metal stress memorization technology 有权
    金属应力记忆技术

    公开(公告)号：US07985652B2

    公开(公告)日：2011-07-26

    申请号：US11855701

    申请日：2007-09-14

    申请人： Chung-Hu Ke ,  Ta-Ming Kuan ,  Chih-Hsin Ko ,  Wen-Chin Lee

    发明人： Chung-Hu Ke ,  Ta-Ming Kuan ,  Chih-Hsin Ko ,  Wen-Chin Lee

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823807 ,  H01L29/665 ,  H01L29/7847

    摘要： A semiconductor device and method for manufacturing a tensile strained NMOS and a compressive strained PMOS transistor pair, wherein a stressor material is sacrificial is disclosed. The method provides for a substrate, which includes a source/drain for an NMOS transistor, and a PMOS transistor. A first barrier layer is formed on the substrate and a first stressor material is formed on the first barrier layer. The first barrier layer is selectively removed from the PMOS transistor. The substrate is flash annealed and the remaining first stressor material and barrier layer is removed from the substrate.

    摘要翻译： 公开了用于制造拉伸应变NMOS和压缩应变PMOS晶体管对的半导体器件和方法，其中应力源材料是牺牲的。 该方法提供了一种衬底，其包括用于NMOS晶体管的源极/漏极和PMOS晶体管。 在基板上形成第一阻挡层，在第一阻挡层上形成第一应力源材料。 从PMOS晶体管选择性地去除第一势垒层。 衬底被闪光退火，剩余的第一应力材料和阻挡层从衬底上去除。

    Metal Stress Memorization Technology
    4.
    发明申请
    Metal Stress Memorization Technology 有权
    金属应力记忆技术

    公开(公告)号：US20090075442A1

    公开(公告)日：2009-03-19

    申请号：US11855701

    申请日：2007-09-14

    申请人： Chung-Hu Ke ,  Ta-Ming Kuan ,  Chih-Hsin Ho ,  Wen-Chin Lee

    发明人： Chung-Hu Ke ,  Ta-Ming Kuan ,  Chih-Hsin Ho ,  Wen-Chin Lee

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L29/665 ,  H01L29/7847

    摘要： A semiconductor device and method for manufacturing a tensile strained NMOS and a compressive strained PMOS transistor pair, wherein a stressor material is sacrificial is disclosed. The method provides for a substrate, which includes a source/drain for an NMOS transistor, and a PMOS transistor. A first barrier layer is formed on the substrate and a first stressor material is formed on the first barrier layer. The first barrier layer is selectively removed from the PMOS transistor. The substrate is flash annealed and the remaining first stressor material and barrier layer is removed from the substrate.

    摘要翻译： 公开了用于制造拉伸应变NMOS和压缩应变PMOS晶体管对的半导体器件和方法，其中应力源材料是牺牲的。 该方法提供了一种衬底，其包括用于NMOS晶体管的源极/漏极和PMOS晶体管。 在基板上形成第一阻挡层，在第一阻挡层上形成第一应力源材料。 从PMOS晶体管选择性地去除第一势垒层。 衬底被闪光退火，剩余的第一应力材料和阻挡层从衬底上去除。

    Methods for forming a transistor with a strained channel
    6.
    发明授权
    Methods for forming a transistor with a strained channel 有权
    用于形成具有应变通道的晶体管的方法

    公开(公告)号：US08236658B2

    公开(公告)日：2012-08-07

    申请号：US12477757

    申请日：2009-06-03

    申请人： Ta-Ming Kuan ,  Chih-Hsin Ko ,  Wen-Chin Lee

    发明人： Ta-Ming Kuan ,  Chih-Hsin Ko ,  Wen-Chin Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

    摘要： A semiconductor device and method for fabricating a semiconductor device providing reduced short channel effects is disclosed. The method comprises providing a substrate comprising a first material; forming at least one gate stack over the substrate; forming one or more recesses in the substrate, wherein the one or more recesses define at least one source region and at least one drain region; and forming a pocket, a first layer comprising a second material, and a second layer comprising a third material in the one or more recesses, the pocket being disposed between the first layer and the substrate.

    摘要翻译： 公开了一种用于制造提供减小的短通道效应的半导体器件的半导体器件和方法。 该方法包括提供包括第一材料的基底; 在所述衬底上形成至少一个栅极堆叠; 在所述衬底中形成一个或多个凹槽，其中所述一个或多个凹部限定至少一个源极区域和至少一个漏极区域; 并且形成袋，包含第二材料的第一层和在所述一个或多个凹部中包含第三材料的第二层，所述袋设置在所述第一层和所述基底之间。

    METHODS FOR FORMING A TRANSISTOR WITH A STRAINED CHANNEL
    7.
    发明申请
    METHODS FOR FORMING A TRANSISTOR WITH A STRAINED CHANNEL 有权
    用于形成具有应变通道的晶体管的方法

    公开(公告)号：US20100308379A1

    公开(公告)日：2010-12-09

    申请号：US12477757

    申请日：2009-06-03

    申请人： Ta-Ming Kuan ,  Chih-Hsin Ko ,  Wen-Chin Lee

    发明人： Ta-Ming Kuan ,  Chih-Hsin Ko ,  Wen-Chin Lee

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

    摘要： A semiconductor device and method for fabricating a semiconductor device providing reduced short channel effects is disclosed. The method comprises providing a substrate comprising a first material; forming at least one gate stack over the substrate; forming one or more recesses in the substrate, wherein the one or more recesses define at least one source region and at least one drain region; and forming a pocket, a first layer comprising a second material, and a second layer comprising a third material in the one or more recesses, the pocket being disposed between the first layer and the substrate.

    摘要翻译： 公开了一种用于制造提供减小的短通道效应的半导体器件的半导体器件和方法。 该方法包括提供包括第一材料的基底; 在所述衬底上形成至少一个栅极堆叠; 在所述衬底中形成一个或多个凹槽，其中所述一个或多个凹部限定至少一个源极区域和至少一个漏极区域; 并且形成袋，包含第二材料的第一层和在所述一个或多个凹部中包含第三材料的第二层，所述袋设置在所述第一层和所述基底之间。

    CMOS Devices with Schottky Source and Drain Regions
    9.
    发明申请
    CMOS Devices with Schottky Source and Drain Regions 有权
    具有肖特基源和漏极区域的CMOS器件

    公开(公告)号：US20110223727A1

    公开(公告)日：2011-09-15

    申请号：US13113530

    申请日：2011-05-23

    申请人： Chih-Hsin Ko ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

    发明人： Chih-Hsin Ko ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/47 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66568 ,  H01L29/6659 ,  H01L29/66643 ,  H01L29/7843

    摘要： A semiconductor structure includes a semiconductor substrate, and an NMOS device at a surface of the semiconductor substrate, wherein the NMOS device comprises a Schottky source/drain extension region. The semiconductor structure further includes a PMOS device at the surface of the semiconductor substrate, wherein the PMOS device comprises a source/drain extension region comprising only non-metal materials. Schottky source/drain extension regions may be formed for both PMOS and NMOS devices, wherein the Schottky barrier height of the PMOS device is reduced by forming the PMOS device over a semiconductor layer having a low valence band.

    摘要翻译： 半导体结构包括半导体衬底和在半导体衬底的表面处的NMOS器件，其中NMOS器件包括肖特基源极/漏极延伸区域。 半导体结构还包括在半导体衬底的表面处的PMOS器件，其中PMOS器件包括仅包含非金属材料的源极/漏极延伸区域。 可以为PMOS器件和NMOS器件形成肖特基源极/漏极延伸区域，其中通过在具有低价带的半导体层上形成PMOS器件来减小PMOS器件的肖特基势垒高度。

    BiCMOS performance enhancement by mechanical uniaxial strain and methods of manufacture
    10.
    发明授权
    BiCMOS performance enhancement by mechanical uniaxial strain and methods of manufacture 有权
    通过机械单轴应变的BiCMOS性能提高和制造方法

    公开(公告)号：US07803718B2

    公开(公告)日：2010-09-28

    申请号：US12260674

    申请日：2008-10-29

    申请人： Chih-Hsin Ko ,  Tzu-Juei Wang ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

    发明人： Chih-Hsin Ko ,  Tzu-Juei Wang ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

    IPC分类号： H01L23/31

    CPC分类号： H01L21/8249 ,  H01L21/823807 ,  H01L27/0623 ,  H01L29/7843

    摘要： A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch stop layer with tensile stress is formed over the NMOS transistor, and a second contact etch stop layer with compressive stress is formed over the PMOS transistor and the bipolar transistor, allowing for an enhancement of each device. Another embodiment has, in addition to the stressed contact etch stop layers, strained channel regions in the PMOS transistor and the NMOS transistor, and a strained base in the BJT.

    摘要翻译： 提供了通过机械单轴应变增强性能的BiCMOS器件。 本发明的第一实施例包括形成在衬底的不同区域上的NMOS晶体管，PMOS晶体管和双极晶体管。 具有拉伸应力的第一接触蚀刻停止层形成在NMOS晶体管上，并且在PMOS晶体管和双极晶体管上形成具有压应力的第二接触蚀刻停止层，从而允许每个器件的增强。 除了应力接触蚀刻停止层之外，另一实施例还包括PMOS晶体管和NMOS晶体管中的应变通道区域以及BJT中的应变基极。