公开(公告)号：US11588452B2

公开(公告)日：2023-02-21

申请号：US17186741

申请日：2021-02-26

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John P. Lesso ,  David P. Singleton

IPC: H03F3/217 ,  H03F1/32

Abstract: Class D amplifier circuitry comprising: modulator circuitry; and output stage circuitry, wherein the modulator circuitry is configured to: receive an input signal and first and second carrier signals, wherein the second carrier signal is offset in amplitude with respect to the first carrier signal; generate first and second modulated output signals, each of the first and second modulated output signals being based on the input signal and the first and second carrier signals; and generate a plurality of control signals for the output stage circuitry per signal period of the modulated output signals, wherein the plurality of control signals are based on the first and second modulated output signals, and wherein at least one of the plurality of control signals per signal period comprises a signal level transition.

公开(公告)号：US11799426B2

公开(公告)日：2023-10-24

申请号：US17537619

申请日：2021-11-30

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Johnny Klarenbeek ,  David P. Singleton ,  Morgan T. Prior ,  Jonathan T. Wigner ,  Christopher M. Dougherty ,  Qi Cai ,  Anindya Bhattacharya

IPC: H03F1/02 ,  H03F3/217 ,  H03F3/38

CPC classification number: H03F1/0233 ,  H03F3/217 ,  H03F2200/03 ,  H03F2200/105

Abstract: Class D amplifier circuitry comprising: input buffer circuitry configured to receive a first digital input signal modulated according to a first modulation scheme in which the digital input signal can take a first plurality N of discrete signal levels; analog modulator circuitry configured to generate an analog modulated signal based on an analog output signal output by the input buffer circuitry; and quantizer circuitry configured to generate an output signal based on the analog modulated signal, wherein the output signal is modulated according to a second modulation scheme in which the output signal can take a second plurality M of discrete signal levels, wherein the second plurality M is greater than the first plurality N.

公开(公告)号：US11528031B2

公开(公告)日：2022-12-13

申请号：US17184295

申请日：2021-02-24

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Andrew J. Howlett ,  David P. Singleton ,  Aniruddha Satoskar

IPC: H03M1/00 ,  H03M1/12 ,  H03F3/217 ,  H03G3/00 ,  H03G9/00 ,  H03M1/08

Abstract: This application relates to ADC circuitry. An ADC circuit (200) has first and second conversion paths (201a, 201b) for converting analogue signals to digital and is operable in first and second modes. In the first mode, the first and second conversion paths are connected to respective first and second input nodes (202a, 202b) to receive and convert full scale first and second analogue input signals (Ain1, Ain2) to separate digital outputs (Dout1, Dout2). In the second mode, the first and second conversion paths are both connected to the first input node (202a), to convert the first analogue input signal (Ain1) to respective first and second digital signals, and the first and second conversion paths are configured for processing different signal levels of the first analogue input signal. A selector (207) select the first digital signal or the second digital to be output as an output signal based on an indication of amplitude of the first analogue input signal.

公开(公告)号：US12283929B2

公开(公告)日：2025-04-22

申请号：US18521667

申请日：2023-11-28

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： David P. Singleton ,  Andrew J. Howlett ,  John B. Bowlerwell

IPC: H03F3/45

Abstract: The present disclosure relates to circuitry comprising audio amplifier circuitry for receiving an audio signal to be amplified; and first and second output nodes for outputting first and second differential output signals. The circuitry further comprises common mode buffer circuitry configured to receive a common mode voltage and to selectively output the common mode voltage to the first and second output nodes.

公开(公告)号：US11881826B2

公开(公告)日：2024-01-23

申请号：US17142904

申请日：2021-01-06

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： David P. Singleton ,  Andrew J. Howlett ,  John B. Bowlerwell

IPC: H03F3/45

CPC classification number: H03F3/45659 ,  H03F3/45179 ,  H03F3/45645 ,  H03F2200/03 ,  H03F2203/45084 ,  H03F2203/45402 ,  H03F2203/45592

Abstract: The present disclosure relates to circuitry comprising audio amplifier circuitry for receiving an audio signal to be amplified; and first and second output nodes for outputting first and second differential output signals. The circuitry further comprises common mode buffer circuitry configured to receive a common mode voltage and to selectively output the common mode voltage to the first and second output nodes.