公开(公告)号：US12002482B2

公开(公告)日：2024-06-04

申请号：US17845703

申请日：2022-06-21

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John Paul Lesso ,  Peter John Frith ,  John Laurence Pennock

IPC: G06F17/00 ,  G10L19/002 ,  G10L19/008 ,  G10L19/16 ,  H04L25/49

CPC classification number: G10L19/167 ,  G10L19/002 ,  G10L19/008 ,  H04L25/49 ,  H04L25/4902 ,  H04L25/4904

Abstract: This application relates to methods and apparatus for transfer of multiple digital data streams, especially of digital audio data over a single communications link such as a single wire. The application describes audio interface circuitry comprising a pulse-length-modulation (PLM) modulator. The PLM is responsive to a plurality of data streams (PDM-R, PDM-L), to generate a series of data pulses (PLM) with a single data pulse having a rising and falling edge in each of a plurality of transfer periods defined by a first clock signal (TCLK). The timing of the rising and falling edge of each data pulse is dependent upon a combination of the then current data samples from the plurality of data streams. The duration and position of the data pulse in the transfer window in effect defines a data symbol encoding the data. Circuitry for receiving and extracting the data is also disclosed. An interface receives the stream of data pulses (PLM) and data extraction circuitry samples the data pulse to determine which of the possible data symbols the pulse represents and determines a data value for at least one received data stream.

公开(公告)号：US11417349B2

公开(公告)日：2022-08-16

申请号：US16803703

申请日：2020-02-27

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John Paul Lesso ,  Peter John Frith ,  John Laurence Pennock

IPC: G06F17/00 ,  G10L19/16 ,  H04L25/49 ,  G10L19/002

Abstract: This application relates to methods and apparatus for transfer of multiple digital data streams, especially of digital audio data over a single communications link such as a single wire. The application describes audio interface circuitry comprising a pulse-length-modulation (PLM) modulator. The PLM is responsive to a plurality of data streams (PDM-R, PDM-L), to generate a series of data pulses (PLM) with a single data pulse having a rising and falling edge in each of a plurality of transfer periods defined by a first clock signal (TCLK). The timing of the rising and falling edge of each data pulse is dependent upon a combination of the then current data samples from the plurality of data streams. The duration and position of the data pulse in the transfer window in effect defines a data symbol encoding the data. Circuitry for receiving and extracting the data is also disclosed. An interface receives the stream of data pulses (PLM) and data extraction circuitry samples the data pulse to determine which of the possible data symbols the pulse represents and determines a data value for at least one received data stream.